Research output per year
Research output per year
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Dive into the research topics where Lucas Moura Santana is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS
Moura Santana, L., Martens, E., Lagos Benites, J. L., Hershberg, B., Wambacq, P. & Craninckx, J., 1 Jul 2022, In: IEEE JOURNAL OF SOLID-STATE CIRCUITS. 57, 7, p. 2068-2077 10 p.Research output: Contribution to journal › Article › peer-review
2 Citations (Scopus) -
A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC
Moura Santana, L., Martens, E., Lagos Benites, J. L., Hershberg, B., Wambacq, P. & Craninckx, J., 13 Sep 2021, ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC). Grenoble, France: IEEE, p. 207-210 4 p. (ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference paper
1 Citation (Scopus)
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HiSilicon Sponsorship for Mini@sic tape-out
Lucas Moura Santana (Participant), Piet Wambacq (Participant) & Johan Stiens (Participant)
16 Jun 2022Activity: Other › Written proposal
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A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC
Lucas Moura Santana (Speaker)
14 Sep 2021Activity: Talk or presentation › Talk or presentation at a conference
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IEEE 47th European Solid State Circuits Conference
Lucas Moura Santana (Participant)
13 Sep 2021 → 17 Sep 2021Activity: Participating in or organising an event › Participation in conference
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HiSilicon Sponsorship Program for MPW Prototyping
Lucas Moura Santana (Participant), Piet Wambacq (Participant) & Johan Stiens (Participant)
5 May 2020Activity: Other › Written proposal