Research output per year
Research output per year
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Dive into the research topics where Nereo Markulic is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
- 1 Similar Profiles
Collaborations and top research areas from the last five years
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Research output
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Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation
Renukaswamy, P., Markulic, N., Wambacq, P. & Craninckx, J., 22 May 2021, Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. Daegu, Korea: Institute of Electrical and Electronics Engineers ( IEEE ), p. 1-5 9401690. (2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)).Research output: Chapter in Book/Report/Conference proceeding › Conference paper › Research
4 Citations (Scopus) -
A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth
Renukaswamy, P., Markulic, N., Wambacq, P. & Craninckx, J., 15 Sep 2020, In: IEEE Journal of Solid - State Circuits. 55, 12, p. 3294-3307 14 p., 9197684.Research output: Contribution to journal › Article › peer-review
23 Citations (Scopus) -
A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp Bandwidth
Renukaswamy, P., Markulic, N., Park, S., Kankuppe Raghavendra Swamy, A., Shi, Q., Wambacq, P. & Craninckx, J., 18 Feb 2020, 2020 International Solid-State Circuits Conference. San Francisco: Institute of Electrical and Electronics Engineers ( IEEE ), p. 278-280 3 p. 17.7Research output: Chapter in Book/Report/Conference proceeding › Conference paper › Research
18 Citations (Scopus) -
A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With-41.3-dB EVM at 1024 QAM in 28-nm CMOS
Markulic, N., Renukaswamy, P. T., Martens, E., van Liempd, B., Wambacq, P. & Craninckx, J., Apr 2019, In: IEEE Journal of Solid-State Circuits. 54, 4, p. 1059-1073 15 p., 8629048.Research output: Contribution to journal › Article › peer-review
22 Citations (Scopus) -
DTC-based PLL and method for operating the DTC-based PLL
Markulic, N., Liu, Y. & Craninckx, J., 2019, Patent No. US10200047Research output: Patent
Activities
- 1 Talk or presentation at a conference
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A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp Bandwidth
Pratap Renukaswamy (Speaker), Nereo Markulic (Contributor), Sehoon Park (Contributor), Anirudh Kankuppe Raghavendra Swamy (Contributor), Qixian Shi (Contributor), Piet Wambacq (Contributor) & Jan Craninckx (Contributor)
18 Feb 2020Activity: Talk or presentation › Talk or presentation at a conference