Design of Low Phase Noise Voltage-Controlled Oscillators in III-V Technologies for 6G Applications

For the upcoming 6G communications, multi-gigabit data rates are targeted. This will be achieved by
operating at higher frequencies than today (7– 24 GHz and 110–170 GHz bands will be considered),
yielding wider bandwidths, but also by implementing complex modulation techniques that require a
high signal-to-noise ratio (SNR) for the transceiver. One of the transceiver components that
constrains the overall performance is the local oscillator, whose phase noise limits the SNR. The
traditional CMOS implementations are reaching their limits due to the low supply voltage that is
required for reliability reasons. This problem will be investigated in this PhD, where low phase noise
voltage-controlled oscillators (VCO) in gallium nitride (GaN) and indium phosphide (InP) will be
designed, as these III-V technologies have a high breakdown voltage in combination with a high
mobility. A high supply voltage, enabling a high voltage swing can yield a low phase noise.
Due to the differences between III-V and CMOS technologies, it is not possible to directly implement
VCO designs previously demonstrated in CMOS. Therefore, it will be investigated how to modify
existing topologies for implementation in III-V technologies and to adapt to high supply voltages.
Also, new techniques will be proposed as well, with emphasis on reducing the upconversion of 1/f
noise and obtaining a wide tuning range. Two different GaN technologies and one InP technology will
be used for four chip designs in total.