Evaluation of deep-sub quarter micrometer CMOS technologies for RF design in wireless applications

The goals of this work are:
- to develop circuit design techniques and circuit optimization methods for RF CMOS design in all operation regimes of the MOS transistor
- to develop circuit optimization techniques for a given power consumption and performance for a given application
- to interact with technology development in order to steer the CMOS technology development towards RF needs, which calls for multi-disciplinary research.
- to investigate the feasibility of realizing RF circuits in future MOS technologies (sub –90 nm CMOS nodes)

I focus on two major building blocks for any RF font-end: a low-noise-amplifier (LNA) with and without Electrostatic discharge (ESD) protection, and voltage-controlled oscillator (VCO).
This work takes place during the development of the IMEC 90 nm RF CMOS technology. The research will be performed during two 90 nm CMOS design cycles, a 0.13 um SiGeC BiCMOS design cycle, and an early 45 nm FinFet design.
During the first 90 nm CMOS RF design, we observed that there was a need for accurate RF design strategies valid in the moderate inversion operation regime. For LNAs these strategies will be developed within this work. A feedback towards technology development was delivered with respect of the use of elevated source/Drain