3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability

A. Vandooren; J. Franco; B. Parvais; Z. Wu; L. Witters; A. Walke; W. Li; L. Peng; V. Deshpande; F. M. Bufler; N. Rassoul; G. Hellings; G. Jamieson; F. Inoue; G. Verbinnen; K. Devriendt; L. Teugels; N. Heylen; E. Vecchio; T. Zheng; E. Rosseel; W. Vanherle; A. Hikavyy; B. T. Chan; R. Ritzenthaler; G. Besnard; W. Schwarzenbach; G. Gaudin; I. Radu; B. Y. Nguyen; N. Waldron; V. De Heyn; D. Mocuta; N. Collaert

doi:10.1109/TED.2018.2871265

3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability

A. Vandooren, J. Franco, B. Parvais, Z. Wu, L. Witters, A. Walke, W. Li, L. Peng, V. Deshpande, F. M. Bufler, N. Rassoul, G. Hellings, G. Jamieson, F. Inoue, G. Verbinnen, K. Devriendt, L. Teugels, N. Heylen, E. Vecchio, T. ZhengE. Rosseel, W. Vanherle, A. Hikavyy, B. T. Chan, R. Ritzenthaler, G. Besnard, W. Schwarzenbach, G. Gaudin, I. Radu, B. Y. Nguyen, N. Waldron, V. De Heyn, D. Mocuta, N. Collaert

Research output: Contribution to journal › Article › peer-review

12 Citations (Scopus)

Abstract

3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 °C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at V _G= V _th+ 0.6 V, 125 °C), even without the use of 'reliability' anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer.

Original language	English
Article number	8487028
Pages (from-to)	5165-5171
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	65
Issue number	11
DOIs	https://doi.org/10.1109/TED.2018.2871265
Publication status	Published - Nov 2018

Keywords

3-D sequential
analog
Annealing
Bonding
Doping
junctionless (JL) devices
Logic gates
low-temperature CMOS
matching
MOS devices
Reliability
RF
Silicon
silicon-on-insulator (SOI)
wafer bonding.

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10.1109/TED.2018.2871265

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Vandooren, A., Franco, J., Parvais, B., Wu, Z., Witters, L., Walke, A., Li, W., Peng, L., Deshpande, V., Bufler, F. M., Rassoul, N., Hellings, G., Jamieson, G., Inoue, F., Verbinnen, G., Devriendt, K., Teugels, L., Heylen, N., Vecchio, E., ... Collaert, N. (2018). 3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability. IEEE Transactions on Electron Devices, 65(11), 5165-5171. [8487028]. https://doi.org/10.1109/TED.2018.2871265

Vandooren, A. ; Franco, J. ; Parvais, B. ; Wu, Z. ; Witters, L. ; Walke, A. ; Li, W. ; Peng, L. ; Deshpande, V. ; Bufler, F. M. ; Rassoul, N. ; Hellings, G. ; Jamieson, G. ; Inoue, F. ; Verbinnen, G. ; Devriendt, K. ; Teugels, L. ; Heylen, N. ; Vecchio, E. ; Zheng, T. ; Rosseel, E. ; Vanherle, W. ; Hikavyy, A. ; Chan, B. T. ; Ritzenthaler, R. ; Besnard, G. ; Schwarzenbach, W. ; Gaudin, G. ; Radu, I. ; Nguyen, B. Y. ; Waldron, N. ; De Heyn, V. ; Mocuta, D. ; Collaert, N. / 3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability. In: IEEE Transactions on Electron Devices. 2018 ; Vol. 65, No. 11. pp. 5165-5171.

@article{cfb3b0ed213a4c73a9651e0d11344d6f,

title = "3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability",

abstract = "3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 °C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at V G= V th+ 0.6 V, 125 °C), even without the use of 'reliability' anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer. ",

keywords = "3-D sequential, analog, Annealing, Bonding, Doping, junctionless (JL) devices, Logic gates, low-temperature CMOS, matching, MOS devices, Reliability, RF, Silicon, silicon-on-insulator (SOI), wafer bonding.",

author = "A. Vandooren and J. Franco and B. Parvais and Z. Wu and L. Witters and A. Walke and W. Li and L. Peng and V. Deshpande and Bufler, {F. M.} and N. Rassoul and G. Hellings and G. Jamieson and F. Inoue and G. Verbinnen and K. Devriendt and L. Teugels and N. Heylen and E. Vecchio and T. Zheng and E. Rosseel and W. Vanherle and A. Hikavyy and Chan, {B. T.} and R. Ritzenthaler and G. Besnard and W. Schwarzenbach and G. Gaudin and I. Radu and Nguyen, {B. Y.} and N. Waldron and {De Heyn}, V. and D. Mocuta and N. Collaert",

year = "2018",

month = nov,

doi = "10.1109/TED.2018.2871265",

language = "English",

volume = "65",

pages = "5165--5171",

journal = "IEEE Trans. Elec. Devs.",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "11",

}

Vandooren, A, Franco, J, Parvais, B, Wu, Z, Witters, L, Walke, A, Li, W, Peng, L, Deshpande, V, Bufler, FM, Rassoul, N, Hellings, G, Jamieson, G, Inoue, F, Verbinnen, G, Devriendt, K, Teugels, L, Heylen, N, Vecchio, E, Zheng, T, Rosseel, E, Vanherle, W, Hikavyy, A, Chan, BT, Ritzenthaler, R, Besnard, G, Schwarzenbach, W, Gaudin, G, Radu, I, Nguyen, BY, Waldron, N, De Heyn, V, Mocuta, D & Collaert, N 2018, '3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability', IEEE Transactions on Electron Devices, vol. 65, no. 11, 8487028, pp. 5165-5171. https://doi.org/10.1109/TED.2018.2871265

3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability. / Vandooren, A.; Franco, J.; Parvais, B.; Wu, Z.; Witters, L.; Walke, A.; Li, W.; Peng, L.; Deshpande, V.; Bufler, F. M.; Rassoul, N.; Hellings, G.; Jamieson, G.; Inoue, F.; Verbinnen, G.; Devriendt, K.; Teugels, L.; Heylen, N.; Vecchio, E.; Zheng, T.; Rosseel, E.; Vanherle, W.; Hikavyy, A.; Chan, B. T.; Ritzenthaler, R.; Besnard, G.; Schwarzenbach, W.; Gaudin, G.; Radu, I.; Nguyen, B. Y.; Waldron, N.; De Heyn, V.; Mocuta, D.; Collaert, N.

In: IEEE Transactions on Electron Devices, Vol. 65, No. 11, 8487028, 11.2018, p. 5165-5171.

Research output: Contribution to journal › Article › peer-review

TY - JOUR

T1 - 3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability

AU - Vandooren, A.

AU - Franco, J.

AU - Parvais, B.

AU - Wu, Z.

AU - Witters, L.

AU - Walke, A.

AU - Li, W.

AU - Peng, L.

AU - Deshpande, V.

AU - Bufler, F. M.

AU - Rassoul, N.

AU - Hellings, G.

AU - Jamieson, G.

AU - Inoue, F.

AU - Verbinnen, G.

AU - Devriendt, K.

AU - Teugels, L.

AU - Heylen, N.

AU - Vecchio, E.

AU - Zheng, T.

AU - Rosseel, E.

AU - Vanherle, W.

AU - Hikavyy, A.

AU - Chan, B. T.

AU - Ritzenthaler, R.

AU - Besnard, G.

AU - Schwarzenbach, W.

AU - Gaudin, G.

AU - Radu, I.

AU - Nguyen, B. Y.

AU - Waldron, N.

AU - De Heyn, V.

AU - Mocuta, D.

AU - Collaert, N.

PY - 2018/11

Y1 - 2018/11

N2 - 3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 °C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at V G= V th+ 0.6 V, 125 °C), even without the use of 'reliability' anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer.

AB - 3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 °C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at V G= V th+ 0.6 V, 125 °C), even without the use of 'reliability' anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer.

KW - 3-D sequential

KW - analog

KW - Annealing

KW - Bonding

KW - Doping

KW - junctionless (JL) devices

KW - Logic gates

KW - low-temperature CMOS

KW - matching

KW - MOS devices

KW - Reliability

KW - RF

KW - Silicon

KW - silicon-on-insulator (SOI)

KW - wafer bonding.

UR - http://www.scopus.com/inward/record.url?scp=85054630668&partnerID=8YFLogxK

U2 - 10.1109/TED.2018.2871265

DO - 10.1109/TED.2018.2871265

M3 - Article

AN - SCOPUS:85054630668

VL - 65

SP - 5165

EP - 5171

JO - IEEE Trans. Elec. Devs.

JF - IEEE Trans. Elec. Devs.

SN - 0018-9383

IS - 11

M1 - 8487028

ER -

3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability

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Keywords

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