A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth

Pratap Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx

Research output: Contribution to journal › Article › peer-review

7 Citations (Scopus)

7 Citations
1 Conference paper

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2020

A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp Bandwidth
Renukaswamy, P., Markulic, N., Park, S., Kankuppe Raghavendra Swamy, A., Shi, Q., Wambacq, P. & Craninckx, J., 18 Feb 2020, 2020 International Solid-State Circuits Conference. San Francisco: Institute of Electrical and Electronics Engineers ( IEEE ), p. 278-280 3 p. 17.7
Research output: Chapter in Book/Report/Conference proceeding › Conference paper

13 Citations (Scopus)