A 410 MS/s 2x interleaved 11bit pipelined SAR ADC in 28nm digital CMOS is presented. Each ADC channel consists of a 6b coarse SAR, a dynamic residue amplifier and a 7b fine SAR and includes an on-chip calibration engine that detects and corrects comparator offsets and amplifier gain errors in the background. The ADC achieves a peak SNDR of 59.8 dB at 410 MS/s for an energy per conversion step of 6.5 fJ.
|Title of host publication||IEEE VLSI Symposium Circuits|
|Number of pages||1|
|Publication status||Published - 12 Jun 2013|
|Name||IEEE VLSI Symposium Circuits|
- pipelined SAR, calibration