A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter

Cheng Hsueh Tsai; Federico Pepe; Giovanni Mangraviti; Zhiwei Zong; Jan Craninckx; Piet Wambacq

doi:10.1109/ESSCIRC.2019.8902868

A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter

Cheng Hsueh Tsai, Federico Pepe, Giovanni Mangraviti, Zhiwei Zong, Jan Craninckx, Piet Wambacq

Research output: Chapter in Book/Report/Conference proceeding › Conference paper

2 Citations (Scopus)

Abstract

We present a 22.5-27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for mm-wave communication. The fast lock is achieved with the help of the proposed gear-shift algorithm,scaling up the PLL bandwidth for faster settling,and orderly reducing it for jitter performance. A digitally controlled oscillator (DCO),based on transformer feedback with a tunable source-bridged capacitor,exhibits low phase noise (PN) over a wide tuning range (FoM of -184 dBc/Hz and FoM_T of -191 dBc/Hz). The PLL occupies 0.09-mm² core area and exhibits 220-fs RMS jitter while consuming 25 mW,giving FoMRMS of -239 dB. Its settling time improves from 780 to 45 μs with our gear-shift algorithm. For 60-GHz communication,with a frequency multiplication factor of 2.5,this PLL covers all six channel frequencies of IEEE-802.11ad and is capable of supporting 128 QAM and beyond.

Original language	English
Title of host publication	ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	111-114
Number of pages	4
ISBN (Electronic)	9781728115504
DOIs	https://doi.org/10.1109/ESSCIRC.2019.8902868
Publication status	Published - 1 Sept 2019
Event	45th IEEE European Solid State Circuits Conference, ESSCIRC 2019 - Cracow, Poland Duration: 23 Sept 2019 → 26 Sept 2019

Publication series

Name	ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference

Conference

Conference	45th IEEE European Solid State Circuits Conference, ESSCIRC 2019
Country/Territory	Poland
City	Cracow
Period	23/09/19 → 26/09/19

Keywords

Fast-lock phase-locked loop (PLL)
IEEE 802.11ad
mm-wave

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10.1109/ESSCIRC.2019.8902868

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Cite this

Tsai, C. H., Pepe, F., Mangraviti, G., Zong, Z., Craninckx, J., & Wambacq, P. (2019). A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter. In ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (pp. 111-114). Article 8902868 (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ESSCIRC.2019.8902868

Tsai, Cheng Hsueh ; Pepe, Federico ; Mangraviti, Giovanni et al. / A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter. ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 111-114 (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference).

@inproceedings{92837a21d76f4350ae631d1df5b68cbe,

title = "A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter",

abstract = "We present a 22.5-27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for mm-wave communication. The fast lock is achieved with the help of the proposed gear-shift algorithm,scaling up the PLL bandwidth for faster settling,and orderly reducing it for jitter performance. A digitally controlled oscillator (DCO),based on transformer feedback with a tunable source-bridged capacitor,exhibits low phase noise (PN) over a wide tuning range (FoM of -184 dBc/Hz and FoMT of -191 dBc/Hz). The PLL occupies 0.09-mm2 core area and exhibits 220-fs RMS jitter while consuming 25 mW,giving FoMRMS of -239 dB. Its settling time improves from 780 to 45 μs with our gear-shift algorithm. For 60-GHz communication,with a frequency multiplication factor of 2.5,this PLL covers all six channel frequencies of IEEE-802.11ad and is capable of supporting 128 QAM and beyond.",

keywords = "Fast-lock phase-locked loop (PLL), IEEE 802.11ad, mm-wave",

author = "Tsai, {Cheng Hsueh} and Federico Pepe and Giovanni Mangraviti and Zhiwei Zong and Jan Craninckx and Piet Wambacq",

year = "2019",

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Tsai, CH, Pepe, F, Mangraviti, G, Zong, Z, Craninckx, J & Wambacq, P 2019, A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter. in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference., 8902868, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 111-114, 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019, Cracow, Poland, 23/09/19. https://doi.org/10.1109/ESSCIRC.2019.8902868

A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter. / Tsai, Cheng Hsueh; Pepe, Federico; Mangraviti, Giovanni et al.
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2019. p. 111-114 8902868 (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference paper

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T1 - A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter

AU - Tsai, Cheng Hsueh

AU - Pepe, Federico

AU - Mangraviti, Giovanni

AU - Zong, Zhiwei

AU - Craninckx, Jan

AU - Wambacq, Piet

PY - 2019/9/1

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N2 - We present a 22.5-27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for mm-wave communication. The fast lock is achieved with the help of the proposed gear-shift algorithm,scaling up the PLL bandwidth for faster settling,and orderly reducing it for jitter performance. A digitally controlled oscillator (DCO),based on transformer feedback with a tunable source-bridged capacitor,exhibits low phase noise (PN) over a wide tuning range (FoM of -184 dBc/Hz and FoMT of -191 dBc/Hz). The PLL occupies 0.09-mm2 core area and exhibits 220-fs RMS jitter while consuming 25 mW,giving FoMRMS of -239 dB. Its settling time improves from 780 to 45 μs with our gear-shift algorithm. For 60-GHz communication,with a frequency multiplication factor of 2.5,this PLL covers all six channel frequencies of IEEE-802.11ad and is capable of supporting 128 QAM and beyond.

AB - We present a 22.5-27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for mm-wave communication. The fast lock is achieved with the help of the proposed gear-shift algorithm,scaling up the PLL bandwidth for faster settling,and orderly reducing it for jitter performance. A digitally controlled oscillator (DCO),based on transformer feedback with a tunable source-bridged capacitor,exhibits low phase noise (PN) over a wide tuning range (FoM of -184 dBc/Hz and FoMT of -191 dBc/Hz). The PLL occupies 0.09-mm2 core area and exhibits 220-fs RMS jitter while consuming 25 mW,giving FoMRMS of -239 dB. Its settling time improves from 780 to 45 μs with our gear-shift algorithm. For 60-GHz communication,with a frequency multiplication factor of 2.5,this PLL covers all six channel frequencies of IEEE-802.11ad and is capable of supporting 128 QAM and beyond.

KW - Fast-lock phase-locked loop (PLL)

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BT - ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019

Y2 - 23 September 2019 through 26 September 2019

ER -

Tsai CH, Pepe F, Mangraviti G, Zong Z, Craninckx J, Wambacq P. A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter. In ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc. 2019. p. 111-114. 8902868. (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference). doi: 10.1109/ESSCIRC.2019.8902868

A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter

Abstract

Publication series

Conference

Keywords

Access to Document

Handle.net

Other files and links

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SRP19: Strategic Research Programme: Center for model-based system improvement - From Computer-Aided Engineering to Model-Aided Engineering

Cite this

A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter

Abstract

Publication series

Conference

Keywords

Access to Document

Handle.net

Other files and links

Fingerprint

Projects

SRP19: Strategic Research Programme: Center for model-based system improvement - From Computer-Aided Engineering to Model-Aided Engineering

Cite this