A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS

Bob Verbruggen, J. Craninckx, Maarten Kuijk, Piet Wambacq, G. Van Der Plas

Research output: Chapter in Book/Report/Conference proceedingConference paperResearch

64 Citations (Scopus)

Abstract

High-speed low-resolution ADCs are an essential part of receivers for wireless standards such as UWB. These converters have to combine the stringent speed specifications with the demand for low power consumption. Flash architectures are often chosen because they offer the largest speed. However, in this architecture, area and power depend exponentially on the resolution since the comparators are often the largest contributor to the overall power consumption. Folding is a well-known technique used to reduce the number of comparators in an ADC while maintaining high speed. It was previously implemented by generating a number of zero crossings with folding amplifiers, often in combination with interpolation or averaging. In this design, a folding factor of 2 is realized as in but with only dynamic power consumption and without using amplifiers. This reduces the number of comparators from 31 to 16 for a 5b resolution.
Original languageEnglish
Title of host publicationISSCC Digest of Technical Papers
PublisherIEEE
Pages252-253
Number of pages2
Volume51
ISBN (Print)978-1-4244-2010-0
Publication statusPublished - 3 Feb 2008
EventFinds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet - Stockholm, Sweden
Duration: 21 Sep 200925 Sep 2009

Conference

ConferenceFinds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet
CountrySweden
CityStockholm
Period21/09/0925/09/09

Keywords

  • ADC
  • high speed
  • folding flash ADC
  • digital CMOS technique
  • wireless standards
  • wireless receivers
  • comparators

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