A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC

Lucas Moura Santana, Ewout Martens, Jorge Luis Lagos Benites, Benjamin Hershberg, Piet Wambacq, Jan Craninckx

Research output: Chapter in Book/Report/Conference proceedingConference paper

1 Citation (Scopus)

Abstract

This work presents a discrete-time (DT) delta sigma modulator (DSM) ADC that uses ring amplifiers to relax critical speed and efficiency bottlenecks. The DSM is designed as a 3 rd -order Cascade of Integrator with Feed Forward (CIFF) with a 4-bit quantizer, and it achieves a peak SNDR of 67dB and DR of 70.0dB with 47.5MHz bandwidth when clocked at 950MHz. This is the highest bandwidth reported to-date among single-channel DT DSM ADCs and demonstrates a viable alternative to continuous-time (CT) DSM ADCs for wideband oversampling applications. With a power consumption of 4.7mW from a 1V supply, FOMs and FOMw are 167.0dB and 27.0fJ/c.s. respectively, demonstrating efficient DT delta-sigma conversion with high bandwidth.
Original languageEnglish
Title of host publicationESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)
Place of PublicationGrenoble, France
PublisherIEEE
Pages207-210
Number of pages4
ISBN (Electronic)9781665437479
DOIs
Publication statusPublished - 13 Sep 2021
EventIEEE 47th European Solid State Circuits Conference - Grenoble, Grenoble, France
Duration: 13 Sep 202117 Sep 2021
https://www.esscirc-essderc2021.org/

Publication series

NameESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings

Conference

ConferenceIEEE 47th European Solid State Circuits Conference
Abbreviated titleESSCIRC
CountryFrance
CityGrenoble
Period13/09/2117/09/21
Internet address

Keywords

  • ADC
  • CMOS
  • delta sigma modulation

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