A 54-64.8 GHz Subharmonically Injection-Locked Frequency Synthesizer with Transmitter EVM between -26.5 dB and -28.8 dB in 28 nm CMOS

Cheng-Hsueh Tsai; Giovanni Mangraviti; Qixian Shi; Khaled Khalaf; André Bourdoux; Piet Wambacq

A 54-64.8 GHz Subharmonically Injection-Locked Frequency Synthesizer with Transmitter EVM between -26.5 dB and -28.8 dB in 28 nm CMOS

Cheng-Hsueh Tsai, Giovanni Mangraviti, Qixian Shi, Khaled Khalaf, André Bourdoux, Piet Wambacq

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › Research

Abstract

The 60 GHz frequency synthesizer presented here demonstrates a transmitter error vector magnitude (EVM) between −28.8 and −26.5 dB, from 54 to 64.8 GHz, in 28 nm digital CMOS technology. This is suitable for IEEE 802.11-2016 communications with coded datarates up to 6.4 Gb/s. Its architecture, based on subharmonic injection locking, is immune to pulling by the power amplifier. A 24 GHz phase-locked loop, designed for low phase noise, locks a 60 GHz quadrature oscillator. The phase noise of the resulting 60 GHz carrier is between −96.5 and −93.8 dBc/Hz at 1 MHz offset. The frequency synthesizer, consuming 107 mW, is integrated and demonstrated with a 60 GHz transmitter front end.

Original language	English
Title of host publication	43rd European Solid-State Circuits Conference
Subtitle of host publication	ESSCIRC
Place of Publication	Leuven
Publisher	IEEE
Pages	243-246
Number of pages	4
Publication status	Published - 2017
Event	43rd European Solid-State Circuits Conference - Leuven, Belgium Duration: 11 Sep 2017 → 14 Sep 2017 https://www.esscirc-essderc2017.org/

Conference

Conference	43rd European Solid-State Circuits Conference
Abbreviated title	ESSCIRC
Country/Territory	Belgium
City	Leuven
Period	11/09/17 → 14/09/17
Internet address	https://www.esscirc-essderc2017.org/

Access to Document

http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8094571

SRP19: Strategic Research Programme: Center for model-based system improvement - From Computer-Aided Engineering to Model-Aided Engineering
Vandersteen, G., Rolain, Y., Wambacq, P., Kuijk, M., Vandersteen, G., Rolain, Y., Wambacq, P. & Kuijk, M.
1/11/12 → 31/10/24
Project: Fundamental

Cite this

@inproceedings{1eaaad4824d5410082a88664b3c28728,

title = "A 54-64.8 GHz Subharmonically Injection-Locked Frequency Synthesizer with Transmitter EVM between -26.5 dB and -28.8 dB in 28 nm CMOS",

abstract = "The 60 GHz frequency synthesizer presented here demonstrates a transmitter error vector magnitude (EVM) between −28.8 and −26.5 dB, from 54 to 64.8 GHz, in 28 nm digital CMOS technology. This is suitable for IEEE 802.11-2016 communications with coded datarates up to 6.4 Gb/s. Its architecture, based on subharmonic injection locking, is immune to pulling by the power amplifier. A 24 GHz phase-locked loop, designed for low phase noise, locks a 60 GHz quadrature oscillator. The phase noise of the resulting 60 GHz carrier is between −96.5 and −93.8 dBc/Hz at 1 MHz offset. The frequency synthesizer, consuming 107 mW, is integrated and demonstrated with a 60 GHz transmitter front end.",

author = "Cheng-Hsueh Tsai and Giovanni Mangraviti and Qixian Shi and Khaled Khalaf and Andr{\'e} Bourdoux and Piet Wambacq",

year = "2017",

language = "English",

pages = "243--246",

booktitle = "43rd European Solid-State Circuits Conference",

publisher = "IEEE",

note = "43rd European Solid-State Circuits Conference, ESSCIRC ; Conference date: 11-09-2017 Through 14-09-2017",

url = "https://www.esscirc-essderc2017.org/",

}

Tsai, C-H, Mangraviti, G, Shi, Q, Khalaf, K, Bourdoux, A & Wambacq, P 2017, A 54-64.8 GHz Subharmonically Injection-Locked Frequency Synthesizer with Transmitter EVM between -26.5 dB and -28.8 dB in 28 nm CMOS. in 43rd European Solid-State Circuits Conference : ESSCIRC. IEEE, Leuven , pp. 243-246, 43rd European Solid-State Circuits Conference, Leuven, Belgium, 11/09/17. <http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8094571>

A 54-64.8 GHz Subharmonically Injection-Locked Frequency Synthesizer with Transmitter EVM between -26.5 dB and -28.8 dB in 28 nm CMOS. / Tsai, Cheng-Hsueh; Mangraviti, Giovanni; Shi, Qixian; Khalaf, Khaled; Bourdoux, André; Wambacq, Piet.

43rd European Solid-State Circuits Conference : ESSCIRC. Leuven : IEEE, 2017. p. 243-246.

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › Research

TY - GEN

T1 - A 54-64.8 GHz Subharmonically Injection-Locked Frequency Synthesizer with Transmitter EVM between -26.5 dB and -28.8 dB in 28 nm CMOS

AU - Tsai, Cheng-Hsueh

AU - Mangraviti, Giovanni

AU - Shi, Qixian

AU - Khalaf, Khaled

AU - Bourdoux, André

AU - Wambacq, Piet

PY - 2017

Y1 - 2017

N2 - The 60 GHz frequency synthesizer presented here demonstrates a transmitter error vector magnitude (EVM) between −28.8 and −26.5 dB, from 54 to 64.8 GHz, in 28 nm digital CMOS technology. This is suitable for IEEE 802.11-2016 communications with coded datarates up to 6.4 Gb/s. Its architecture, based on subharmonic injection locking, is immune to pulling by the power amplifier. A 24 GHz phase-locked loop, designed for low phase noise, locks a 60 GHz quadrature oscillator. The phase noise of the resulting 60 GHz carrier is between −96.5 and −93.8 dBc/Hz at 1 MHz offset. The frequency synthesizer, consuming 107 mW, is integrated and demonstrated with a 60 GHz transmitter front end.

AB - The 60 GHz frequency synthesizer presented here demonstrates a transmitter error vector magnitude (EVM) between −28.8 and −26.5 dB, from 54 to 64.8 GHz, in 28 nm digital CMOS technology. This is suitable for IEEE 802.11-2016 communications with coded datarates up to 6.4 Gb/s. Its architecture, based on subharmonic injection locking, is immune to pulling by the power amplifier. A 24 GHz phase-locked loop, designed for low phase noise, locks a 60 GHz quadrature oscillator. The phase noise of the resulting 60 GHz carrier is between −96.5 and −93.8 dBc/Hz at 1 MHz offset. The frequency synthesizer, consuming 107 mW, is integrated and demonstrated with a 60 GHz transmitter front end.

M3 - Conference paper

SP - 243

EP - 246

BT - 43rd European Solid-State Circuits Conference

PB - IEEE

CY - Leuven

T2 - 43rd European Solid-State Circuits Conference

Y2 - 11 September 2017 through 14 September 2017

ER -

A 54-64.8 GHz Subharmonically Injection-Locked Frequency Synthesizer with Transmitter EVM between -26.5 dB and -28.8 dB in 28 nm CMOS

Abstract

Conference

Access to Document

Projects

SRP19: Strategic Research Programme: Center for model-based system improvement - From Computer-Aided Engineering to Model-Aided Engineering

Cite this