A 54-64.8 GHz Subharmonically Injection-Locked Frequency Synthesizer with Transmitter EVM between -26.5 dB and -28.8 dB in 28 nm CMOS

Cheng-Hsueh Tsai, Giovanni Mangraviti, Qixian Shi, Khaled Khalaf, André Bourdoux, Piet Wambacq

Research output: Chapter in Book/Report/Conference proceedingConference paper

Abstract

The 60 GHz frequency synthesizer presented here demonstrates a transmitter error vector magnitude (EVM) between −28.8 and −26.5 dB, from 54 to 64.8 GHz, in 28 nm digital CMOS technology. This is suitable for IEEE 802.11-2016 communications with coded datarates up to 6.4 Gb/s. Its architecture, based on subharmonic injection locking, is immune to pulling by the power amplifier. A 24 GHz phase-locked loop, designed for low phase noise, locks a 60 GHz quadrature oscillator. The phase noise of the resulting 60 GHz carrier is between −96.5 and −93.8 dBc/Hz at 1 MHz offset. The frequency synthesizer, consuming 107 mW, is integrated and demonstrated with a 60 GHz transmitter front end.
Original languageEnglish
Title of host publication43rd European Solid-State Circuits Conference
Subtitle of host publicationESSCIRC
Place of PublicationLeuven
PublisherIEEE
Pages243-246
Number of pages4
Publication statusPublished - 2017
Event43rd European Solid-State Circuits Conference - Leuven, Belgium
Duration: 11 Sep 201714 Sep 2017
https://www.esscirc-essderc2017.org/

Conference

Conference43rd European Solid-State Circuits Conference
Abbreviated titleESSCIRC
CountryBelgium
CityLeuven
Period11/09/1714/09/17
Internet address

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