A 5ps resolution, 8.6ns delay range digital delay line using combinatorial redundancy

Thomas Van Den Dries; Hans Ingelberts; Sven Boulanger; Maarten Kuijk

A 5ps resolution, 8.6ns delay range digital delay line using combinatorial redundancy

Thomas Van Den Dries, Hans Ingelberts, Sven Boulanger, Maarten Kuijk

Research output: Chapter in Book/Report/Conference proceeding › Conference paper

Abstract

A novel digital delay line architecture is presented, which is able to achieve a high resolution of 5 ps and a wide delay range of 8.6 ns simultaneously. It does so by combining elements of digital and analog delay locked loops and uses a replica circuit to compensate for temperature variations. Furthermore, accurate and precise delay steps with 3.8 ps RMS jitter are obtained by using combinatorial redundancy. Its overall performance is superior to state-of-the-art approaches, which make a trade-off for at least one of the performance metrics.

Original language	English
Title of host publication	2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)
Publisher	IEEE
Pages	21-24
Number of pages	4
Publication status	Published - 5 Aug 2019
Event	15th Conference on PhD Research in Microelectronics and Electronics - EPFL, École polytechnique fédérale de Lausanne, Lausanne, Switzerland Duration: 15 Jul 2019 → 18 Jul 2019 https://www.prime2019.com/docs/PRIME19_CFP.pdf

Conference

Conference	15th Conference on PhD Research in Microelectronics and Electronics
Abbreviated title	PRIME2019
Country/Territory	Switzerland
City	Lausanne
Period	15/07/19 → 18/07/19
Internet address	https://www.prime2019.com/docs/PRIME19_CFP.pdf

Handle.net

Persistent link

SRP19: Strategic Research Programme: Center for model-based system improvement - From Computer-Aided Engineering to Model-Aided Engineering
Vandersteen, G. (Administrative Promotor), Rolain, Y. (Co-Promotor), Wambacq, P. (Co-Promotor), Kuijk, M. (Co-Promotor), Vandersteen, G. (Administrative Promotor), Rolain, Y. (Co-Promotor), Wambacq, P. (Co-Promotor) & Kuijk, M. (Co-Promotor)
1/11/12 → 31/10/24
Project: Fundamental

Cite this

@inproceedings{ad6ccb525f3947b583cbd72a42266c6d,

title = "A 5ps resolution, 8.6ns delay range digital delay line using combinatorial redundancy",

abstract = "A novel digital delay line architecture is presented, which is able to achieve a high resolution of 5 ps and a wide delay range of 8.6 ns simultaneously. It does so by combining elements of digital and analog delay locked loops and uses a replica circuit to compensate for temperature variations. Furthermore, accurate and precise delay steps with 3.8 ps RMS jitter are obtained by using combinatorial redundancy. Its overall performance is superior to state-of-the-art approaches, which make a trade-off for at least one of the performance metrics.",

author = "{Van Den Dries}, Thomas and Hans Ingelberts and Sven Boulanger and Maarten Kuijk",

year = "2019",

month = aug,

day = "5",

language = "English",

pages = "21--24",

booktitle = "2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)",

publisher = "IEEE",

note = "15th Conference on PhD Research in Microelectronics and Electronics, PRIME2019 ; Conference date: 15-07-2019 Through 18-07-2019",

url = "https://www.prime2019.com/docs/PRIME19_CFP.pdf",

}

TY - GEN

T1 - A 5ps resolution, 8.6ns delay range digital delay line using combinatorial redundancy

AU - Van Den Dries, Thomas

AU - Ingelberts, Hans

AU - Boulanger, Sven

AU - Kuijk, Maarten

PY - 2019/8/5

Y1 - 2019/8/5

N2 - A novel digital delay line architecture is presented, which is able to achieve a high resolution of 5 ps and a wide delay range of 8.6 ns simultaneously. It does so by combining elements of digital and analog delay locked loops and uses a replica circuit to compensate for temperature variations. Furthermore, accurate and precise delay steps with 3.8 ps RMS jitter are obtained by using combinatorial redundancy. Its overall performance is superior to state-of-the-art approaches, which make a trade-off for at least one of the performance metrics.

AB - A novel digital delay line architecture is presented, which is able to achieve a high resolution of 5 ps and a wide delay range of 8.6 ns simultaneously. It does so by combining elements of digital and analog delay locked loops and uses a replica circuit to compensate for temperature variations. Furthermore, accurate and precise delay steps with 3.8 ps RMS jitter are obtained by using combinatorial redundancy. Its overall performance is superior to state-of-the-art approaches, which make a trade-off for at least one of the performance metrics.

M3 - Conference paper

SP - 21

EP - 24

BT - 2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)

PB - IEEE

T2 - 15th Conference on PhD Research in Microelectronics and Electronics

Y2 - 15 July 2019 through 18 July 2019

ER -

A 5ps resolution, 8.6ns delay range digital delay line using combinatorial redundancy

Abstract

Conference

Handle.net

Fingerprint

Projects

SRP19: Strategic Research Programme: Center for model-based system improvement - From Computer-Aided Engineering to Model-Aided Engineering

Cite this