A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS

Annachiara Spagnolo, Bob Verbruggen, Stefano D'amico, Piet Wambacq

Research output: Chapter in Book/Report/Conference proceedingConference paper

8 Citations (Scopus)


A 7b time interleaved hybrid ADC in 40nm CMOS is presented. The ADC consists of two pipelined stages and combines an intrinsically linear SAR with a fully calibrated binary search architecture to achieve energy efficiency. The first stage of each channel consists of a 3b SAR followed by a dynamic amplifier merged with a comparator. The second stage is a 3b comparator-based asynchronous binary search with threshold calibration to compensate amplifier nonlinearity. The calibration references are generated on chip by using the DAC embedded in the first stage. The prototype achieves a peak SNDR of 38dB at 3.5GS/s while consuming approximately 6.2mW.
Original languageEnglish
Title of host publicationEuropean Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th
ISBN (Electronic)978-1-4799-5696-8
ISBN (Print)978-1-4799-5694-4
Publication statusPublished - 2014
EventEuropean Solid State Circuits Conference (ESSCIRC) - Venice Lido, Italy
Duration: 22 Sep 201426 Sep 2014


ConferenceEuropean Solid State Circuits Conference (ESSCIRC)
Abbreviated titleESSCIRC 2014
CityVenice Lido


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