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A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range

  • Badr Malki
  • , Takaya Yamamoto
  • , Bob Verbruggen
  • , Piet Wambacq
  • , J. Craninckx

Research output: Contribution to journal › Article › peer-review

47 Citations (Scopus)

Abstract

A charge-domain SAR ADC is presented which integrates the current of a variable-gain transconductor on its sampling capacitor, rather than being driven by a power hungry voltage buffer. The sampling circuit uses nonlinear MOS capacitors as sampling capacitor for passive amplification to relax the comparator noise requirements without compromising linearity. The prototype in 40 nm low power CMOS process consists of a 1.1-17.6 mS transconductor, combined with a 10 b 0-80 MS/s charge-sharing SAR ADC. It achieves 70 dB DR while consuming less than 5.45 mA from a 1.1 V supply and achieves a peak SNDR of 56.85 dB at 40 MS/s.
Original languageEnglish
Pages (from-to)1173 - 1183
JournalIEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume49
Issue number5
DOIs
Publication statusPublished - 5 May 2014

Keywords

  • ADC charge based buffer receiver passive amplifica

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