A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range

Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, J. Craninckx

Research output: Chapter in Book/Report/Conference proceedingConference paperResearch

23 Citations (Scopus)

Abstract

This paper presents a charge-domain SAR ADC which integrates the current of a variable-gain transconductor on its sampling capacitor, rather than being driven by a power hungry voltage buffer. The sampling circuit uses nonlinear MOS capacitors for passive amplification, without compromising linearity. The prototype in 40nm LP CMOS consists of a 1.1-17.6mS transconductor, combined with a 10b 0-80MS/s charge-sharing SAR ADC. It achieves 70 dB DR while consuming less than 5.45mA from a 1.1V supply.
Original languageEnglish
Title of host publication2012 IEEE International Solid-State Circuits Conference
Subtitle of host publicationDigest of technical papers
Place of PublicationSt. Louis, Missouri
PublisherIEEE
Pages470-471
Number of pages2
ISBN (Print)978-1-4673-0373-6
Publication statusPublished - 19 Feb 2012
Event2012 IEEE International Solid-State Circuits Conference (ISSCC) - San Francisco, CA, United States
Duration: 19 Feb 201223 Feb 2012

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume55
ISSN (Print)0193-6530

Conference

Conference2012 IEEE International Solid-State Circuits Conference (ISSCC)
CountryUnited States
CitySan Francisco, CA
Period19/02/1223/02/12

Keywords

  • ADC VGA Tranisotor capacitance amplification DAC
  • Comparator fully dynamic SNDR SFDR

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