A data recovery delay-locked loop (DLL) for non-return-to-zero (NRZ) data transmission is described. A reference clock is delayed for triggering a latch that samples the incoming NRZ data stream. The data rate can be twice the reference clock frequency. The circuit has a proportional nondead-zone sampling phase detector that also serves the role of charge pump. A self-correcting function reduces the problem of the finite phase capture range associated with conventional DLLs. The prototype circuit is fabricated in 2.5-V 0.25-mum CMOS and occupies an area of only 270 x 50 mum(2). It is demonstrated that at 900-Mb/s NRZ data, jitter is reduced from 118.2- to 31.3-ps rms jitter for a power consumption of only 3 mW
|Number of pages||5|
|Journal||IEEE JOURNAL OF SOLID-STATE CIRCUITS|
|Publication status||Published - 1 Jun 2002|
Bibliographical notejournal of solid-state circuits, Vol. 27, pp. 711-715.
- PHASE-LOCKED LOOP
- phase detector