A Fault-Tolerant Dual Active Bridge Architecture with Enhanced SoC Balancing Control

Research output: Chapter in Book/Report/Conference proceedingConference paper

2 Downloads (Pure)

Abstract

Electric vehicles (EVs) require cell balancing circuits to equalize the state of charge (SoC) of series-connected cells and to regulate the low-voltage (LV) DC bus using integrated BMS/DC- DC converters. However, most existing integrated BMS/DC-DC converters lack fault-tolerant capabilities, particularly in the presence of hardware-level failures such as open-circuit faults (OCFs). In this paper, a fault-tolerant balancing system controller for an integrated BMS/DC-DC dual-active bridge (DAB) converter, which is capable of simultaneously equalizing the SoC across battery modules and regulating the LV DC bus voltage under both fault-free and post-fault conditions, is proposed. The control strategy enables SoC balancing and voltage regulation through a modified cascade loop that integrates SoC-aware current reference correction. The system is designed to tolerate OCF through control and structural reconfiguration of the DAB, ensuring continued operation. Balancing is achieved by transferring maximum power to minimize the balancing time under both normal and fault conditions. A mathematical model is developed to show the impact of OCFs on the balancing performance, demonstrating that the balancing time increases depending on the fault location. To validate the viability of the controller and to evaluate how OCFs can impact the balancing time, simulation results are presented for both fault-free and post-fault scenarios, highlighting its potential for reliable and efficient integration into battery management systems. Additionally, the balancing time in the fault-free scenario is compared with that of the conventional method, showing an approximate 78% reduction.
Original languageEnglish
Title of host publication2025 14th International Symposium on Advanced Topics in Electrical Engineering (ATEE)
PublisherIEEE Explore
Pages1-6
Number of pages6
ISBN (Electronic)979-8-3315-2646-7
ISBN (Print)979-8-3315-2647-4
DOIs
Publication statusPublished - 29 Dec 2025
Event2025 14th International Symposium on Advanced Topics in Electrical Engineering (ATEE) - Romania, Bucharest, Romania
Duration: 9 Oct 202511 Oct 2025

Conference

Conference2025 14th International Symposium on Advanced Topics in Electrical Engineering (ATEE)
Country/TerritoryRomania
CityBucharest
Period9/10/2511/10/25

Bibliographical note

Publisher Copyright:
© 2025 IEEE.

Keywords

  • Active balancing circuit
  • dual-active bridge
  • fault tolerance
  • open-circuit fault
  • SoC balancing

Fingerprint

Dive into the research topics of 'A Fault-Tolerant Dual Active Bridge Architecture with Enhanced SoC Balancing Control'. Together they form a unique fingerprint.

Cite this