An on-chip reference generator is conceived by adopting the technique of decimating a pseudo-random binary sequence (PRBS) signal in parallel sequences. This is of great benefit when high-speed generation of PRBS and PRBS-derived signals is the objective. The design implemented standard CMOS logic is available in commercial libraries to provide the logic functions for the generator. The design allows the user to select the periodicity of the PRBS and the PRBS-derived signals. The characterization of the on-chip generator marks its performance and reveals promising specifications.
|Number of pages||14|
|Journal||Measurement Science and Technology|
|Publication status||Published - 1 Jun 2011|
- nonlinear measurements
- phase calibration
- pseudo-random binary sequences
- on-chip design