A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks

Bruno Da Silva Gomez; Laurent Segers; An Braeken; Kris Steenhaut; Abdellah Touhafi

doi:10.1007/978-3-319-78890-6_23

A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks

Bruno Da Silva Gomez, Laurent Segers, An Braeken, Kris Steenhaut, Abdellah Touhafi

Research output: Chapter in Book/Report/Conference proceeding › Conference paper

9 Citations (Scopus)

Abstract

Microphone arrays add an extra dimension to sensory information from Wireless Sensor Networks by determining the direction of the sound instead of only its intensity. Microphone arrays, however, need to be flexible enough to adapt their characteristics to realistic acoustic environments, while being power efficient, as they are battery-powered. Consequently, there is a clear need to design adaptable microphone array nodes enabling quality aware distributed sensing and prioritizing low power consumption. In this paper a novel dynamic, scalable and energy-efficient FPGA-based architecture is presented. The proposed architecture applies the Delay-and-Sum beamforming technique to the single-bit digital audio from the MEMS microphones to obtain the relative sound power in the time domain. As a result, the resource consumption is drastically reduced, making the proposed architecture suitable for low-power Flash-based FPGAs. In fact, the architecture’s power consumption estimation can become as low as 649 μW per microphone.

Original language	English
Title of host publication	International Symposium on Applied Reconfigurable Computing
Subtitle of host publication	Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings
Editors	Nikolaos Voros, Georgios Keramidas, Christos Antonopoulos, Michael Huebner, Pedro C. Diniz, Diana Goehringer
Pages	281-293
Number of pages	13
ISBN (Electronic)	978-3-319-78890-6
DOIs	https://doi.org/10.1007/978-3-319-78890-6_23
Publication status	Published - 31 May 2018
Event	International Symposium on Applied Reconfigurable Computing - Santorini, Fira, Greece Duration: 2 May 2018 → 4 May 2018 Conference number: 14 http://arc2018.esda-lab.cied.teiwest.gr/

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	10824 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	International Symposium on Applied Reconfigurable Computing
Abbreviated title	ARC
Country/Territory	Greece
City	Fira
Period	2/05/18 → 4/05/18
Internet address	http://arc2018.esda-lab.cied.teiwest.gr/

Access to Document

10.1007/978-3-319-78890-6_23

Cite this

Da Silva Gomez, B., Segers, L., Braeken, A., Steenhaut, K., & Touhafi, A. (2018). A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks. In N. Voros, G. Keramidas, C. Antonopoulos, M. Huebner, P. C. Diniz, & D. Goehringer (Eds.), International Symposium on Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings (pp. 281-293). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 10824 LNCS). https://doi.org/10.1007/978-3-319-78890-6_23

Da Silva Gomez, Bruno ; Segers, Laurent ; Braeken, An et al. / A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks. International Symposium on Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. editor / Nikolaos Voros ; Georgios Keramidas ; Christos Antonopoulos ; Michael Huebner ; Pedro C. Diniz ; Diana Goehringer. 2018. pp. 281-293 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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title = "A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks",

abstract = "Microphone arrays add an extra dimension to sensory information from Wireless Sensor Networks by determining the direction of the sound instead of only its intensity. Microphone arrays, however, need to be flexible enough to adapt their characteristics to realistic acoustic environments, while being power efficient, as they are battery-powered. Consequently, there is a clear need to design adaptable microphone array nodes enabling quality aware distributed sensing and prioritizing low power consumption. In this paper a novel dynamic, scalable and energy-efficient FPGA-based architecture is presented. The proposed architecture applies the Delay-and-Sum beamforming technique to the single-bit digital audio from the MEMS microphones to obtain the relative sound power in the time domain. As a result, the resource consumption is drastically reduced, making the proposed architecture suitable for low-power Flash-based FPGAs. In fact, the architecture{\textquoteright}s power consumption estimation can become as low as 649 μW per microphone.",

author = "{Da Silva Gomez}, Bruno and Laurent Segers and An Braeken and Kris Steenhaut and Abdellah Touhafi",

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Da Silva Gomez, B , Segers, L , Braeken, A , Steenhaut, K & Touhafi, A 2018, A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks. in N Voros, G Keramidas, C Antonopoulos, M Huebner, PC Diniz & D Goehringer (eds), International Symposium on Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 10824 LNCS, pp. 281-293, International Symposium on Applied Reconfigurable Computing, Fira, Greece, 2/05/18. https://doi.org/10.1007/978-3-319-78890-6_23

A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks. / Da Silva Gomez, Bruno ; Segers, Laurent ; Braeken, An et al.
International Symposium on Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. ed. / Nikolaos Voros; Georgios Keramidas; Christos Antonopoulos; Michael Huebner; Pedro C. Diniz; Diana Goehringer. 2018. p. 281-293 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 10824 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference paper

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T1 - A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks

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AU - Braeken, An

AU - Steenhaut, Kris

AU - Touhafi, Abdellah

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PY - 2018/5/31

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N2 - Microphone arrays add an extra dimension to sensory information from Wireless Sensor Networks by determining the direction of the sound instead of only its intensity. Microphone arrays, however, need to be flexible enough to adapt their characteristics to realistic acoustic environments, while being power efficient, as they are battery-powered. Consequently, there is a clear need to design adaptable microphone array nodes enabling quality aware distributed sensing and prioritizing low power consumption. In this paper a novel dynamic, scalable and energy-efficient FPGA-based architecture is presented. The proposed architecture applies the Delay-and-Sum beamforming technique to the single-bit digital audio from the MEMS microphones to obtain the relative sound power in the time domain. As a result, the resource consumption is drastically reduced, making the proposed architecture suitable for low-power Flash-based FPGAs. In fact, the architecture’s power consumption estimation can become as low as 649 μW per microphone.

AB - Microphone arrays add an extra dimension to sensory information from Wireless Sensor Networks by determining the direction of the sound instead of only its intensity. Microphone arrays, however, need to be flexible enough to adapt their characteristics to realistic acoustic environments, while being power efficient, as they are battery-powered. Consequently, there is a clear need to design adaptable microphone array nodes enabling quality aware distributed sensing and prioritizing low power consumption. In this paper a novel dynamic, scalable and energy-efficient FPGA-based architecture is presented. The proposed architecture applies the Delay-and-Sum beamforming technique to the single-bit digital audio from the MEMS microphones to obtain the relative sound power in the time domain. As a result, the resource consumption is drastically reduced, making the proposed architecture suitable for low-power Flash-based FPGAs. In fact, the architecture’s power consumption estimation can become as low as 649 μW per microphone.

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SN - 978-3-319-78889-0

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

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T2 - International Symposium on Applied Reconfigurable Computing

Y2 - 2 May 2018 through 4 May 2018

ER -

Da Silva Gomez B , Segers L , Braeken A , Steenhaut K , Touhafi A. A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks. In Voros N, Keramidas G, Antonopoulos C, Huebner M, Diniz PC, Goehringer D, editors, International Symposium on Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. 2018. p. 281-293. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-319-78890-6_23

A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks

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