A power reduction method for off-chip interconnects

Research output: Chapter in Book/Report/Conference proceedingConference paperResearch

Abstract

Off-chip interconnects with a length between 5 and 20 cm can typically be modeled as lumped capacitors for operating speeds up to 50-250 MHz. These capacitors can be driven in such a way that their energy is recycled, reducing the power dissipation. This can be achieved by one or more inductors that are included at the driving side allowing energy transfer from the logic level changing interconnects to the inductors and back. Since most of the energy is recycled, the dissipation for changing logic level is reduced considerably. The method is verified first on circuits designed in 0.5 micron CMOS at Vcc=3.3 V, rendering power reduction to 48% of conventional drivers at 10 MHz operating frequency and reduction to 58% at 40 MHz
Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems.Emerging Technologies for the 21st Century.
PublisherPresses Polytech. Univ. Romandes, Lausanne, Switzerl
Pages265-268
Number of pages4
Volume4
ISBN (Print)0-7803-5482-6
Publication statusPublished - 28 May 2000
EventUnknown -
Duration: 28 May 2000 → …

Conference

ConferenceUnknown
Period28/05/00 → …

Bibliographical note

IEEE International Symposium on Circuits and Systems.Emerging Technologies for the 21st Century., Vol. 4, pp. 265-268.

Keywords

  • CMOS digital integrated circuits
  • driver circuits
  • interconnections

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