A Stacked Segmented Adaptive Power Amplifier in 22nm FD-SOI

Aritra Banerjee, Barend van Liempd, Piet Wambacq

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)

Abstract

This letter presents a two-stage mm-wave power amplifier (PA) in 22nm fully depleted silicon-on-insulator (FD-SOI) technology. High output power is obtained through transistor stacking. Transistor segmentation and back-gate bias control techniques are used in this adaptive PA which can work in high gain mode (HGM) and high linearity mode (HLM). The proposed PA achieves 17.9 dBm saturated output power ( Psat ), 27.6 dB power gain, 11.6 dBm output 1-dB compression point (OP1dB), and 11.0% peak power-added efficiency (PAE) at 74 GHz in the HGM. In the HLM, 17.1 dBm Psat , 21.2 dB power gain, 14.6 dBm OP1dB, and 12.9% peak PAE are obtained at 74 GHz.
Original languageEnglish
Pages (from-to)983-986
Number of pages4
JournalIEEE Microwave and Wireless Components Letters
Volume32
Issue number8
DOIs
Publication statusPublished - 1 Aug 2022

Bibliographical note

Publisher Copyright:
© 2001-2012 IEEE.

Copyright:
Copyright 2022 Elsevier B.V., All rights reserved.

Keywords

  • Transistors
  • Gain
  • Power generation
  • Logic gates
  • Voltage measurement
  • Linearity
  • Threshold voltage
  • Fully depleted silicon-on-insulator (FD-SOI)
  • millimeter-wave (mm-wave)
  • power amplifier (PA)

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