Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication

Cheng-Hsueh Tsai, Zhiwei Zong, Federico Pepe, Giovanni Mangraviti, Jan Craninckx, Piet Wambacq

Research output: Contribution to journalArticlepeer-review

14 Citations (Scopus)


This article analyses and demonstrates a 22.5–27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for millimeter-wave (mm-wave) communication. A discrete-time PLL model, together with theoretical transfer functions, gives insight on the functionality of the automatic bandwidth control, on the effect of the gear-shift algorithm for fast lock and on the different noise contributions. The proposed gear-shift algorithm scales up the PLL bandwidth for faster acquisition and orderly reduces it for jitter performance. The PLL contains a digitally controlled oscillator (DCO) based on transformer feedback with a tunable source-bridged capacitor, which allows for a low phase noise (PN) over a wide tuning range (FoM of −184 dBc/Hz and FoM T of −191 dBc/Hz) and for a fine frequency resolution. The PLL occupies 0.09-mm 2 core area and exhibits 220 fs rms jitter while consuming 25 mW, giving FoM RMS of −239 dB. Its frequency acquisition time improves from 780 to 45 μs with the gear-shift algorithm. For 60-GHz communication, with a frequency multiplication factor of 2.5, this PLL covers all six channels’ frequencies of IEEE-802.11ad, allows a transmitter (TX) error vector magnitude (EVM) down to −35.9 dB assuming a TX signal to the noise-plus-distortion ratio (SNDR) of 40 dB, and, thus, is capable of supporting 256 quadrature amplitude modulation (QAM).
Original languageEnglish
Article number9097192
Pages (from-to)1854-1863
Number of pages10
Issue number7
Publication statusPublished - 20 May 2020


  • CMOS


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