Design and Analysis of a 140-GHz T/R Front-End Module in 22-nm FD-SOI CMOS

Xinyan Tang, Johan Nguyen, Giovanni Mangraviti, Zhiwei Zong, Piet Wambacq

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

This article presents novel methodologies and practical design considerations for a D -band transmit/receive (T/R) front-end module (FEM) in 22-nm fully depleted silicon-on-insulator (FD-SOI/FDX) CMOS technology for beyond-5G wireless communication. An ABCD-matrix-based synthesis methodology is proposed to co-design the T/R switch (SW) topology, including the power amplifier (PA) output and the low noise amplifier (LNA) input matching networks, to minimize the losses in both Tx and Rx modes. Based on this synthesis, an asymmetric T/R SW topology is realized with intrinsic electrostatic discharge (ESD) protection. Both the stacked-field-effect transistor (FET) PA and LNA adopt differential topologies with transformer-based matching networks to eliminate unwanted effects from common-mode parasitics. Passive gain-boosting techniques are used for both PA and LNA to enhance different TRx specifications. A reusable unit-cell layout strategy is applied for transistor arrays to accelerate the multiple-stage PA implementation and maintain uniform performance and minimal parasitics. At 140 GHz, the Tx achieves a power gain Gp of 33.6/35.7 dB, a saturated output power Psat of 12.5/14.7 dBm, a peak power-added efficiency (PAE) of 10.8/11.3%, and an output 1-dB compression point (OP1dB) of 9.4/11.2 dBm with nominal/boosted supplies. An average output power (Poutavg)/PAE of 4.9 dBm/2% is obtained for a 4-GHz bandwidth 64-QAM single-carrier signal at an error-vector magnitude (EVM) of -24.8 dB. Moreover, its Tx-mode reliability has been assessed. At 140 GHz, the Rx achieves a 20-dB Gp, a -24-dBm input 1-dB compression point (IP1dB), and a 9.2-dB noise figure (NF) with only 20-mW power consumption from a 0.8-V supply. This compact FEM has a PA/LNA core area of 0.024/0.032 mm2, respectively.

Original languageEnglish
Pages (from-to)1300-1313
Number of pages14
JournalIEEE Journal of Solid-State Circuits
Volume57
Issue number5
DOIs
Publication statusPublished - May 2022

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