Device-, Circuit-Block-level evaluation of CFET in a 4 track library

P. Schuddinck; O. Zografos; P. Weckx; P. Matagne; S. Sarkar; Y. Sherazi; R. Baert; D. Jang; D. Yakimets; A. Gupta; B. Parvais; J. Ryckaert; D. Verkest; A. Mocuta

doi:10.23919/VLSIT.2019.8776513

Device-, Circuit-Block-level evaluation of CFET in a 4 track library

P. Schuddinck, O. Zografos, P. Weckx, P. Matagne, S. Sarkar, Y. Sherazi, R. Baert, D. Jang, D. Yakimets, A. Gupta, B. Parvais, J. Ryckaert, D. Verkest, A. Mocuta

Research output: Chapter in Book/Report/Conference proceeding › Conference paper

68 Citations (Scopus)

Abstract

The structure of the complementary FET (CFET) with NMOS stacked on top of PMOS, inherently yields standard cells and SRAM cells with 25% smaller layout area, 25% higher pin density and 2x higher routing flexibility than FinFET with same overall active footprint. Moreover, our work, based on advanced modelling, demonstrates that 4 track CFET can match and even outperform 5 track FinFET; without the need to lower S/D contact resistivity down to 5e-10Ωcm² or to elevate the channel stress up to 2GPa. All gains in power-performance-area at circuit-level are maintained at block-level, making 4 track CFET a suitable candidate for N3 N2 technologies. Keywords: CFET, scaling, S/D engineering, Pi-gate.

Original language	English
Title of host publication	2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	T204-T205
ISBN (Electronic)	9784863487178
DOIs	https://doi.org/10.23919/VLSIT.2019.8776513
Publication status	Published - 1 Jun 2019
Event	39th Symposium on VLSI Technology, VLSI Technology 2019 - Kyoto, Japan Duration: 9 Jun 2019 → 14 Jun 2019

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2019-June
ISSN (Print)	0743-1562

Conference

Conference	39th Symposium on VLSI Technology, VLSI Technology 2019
Country/Territory	Japan
City	Kyoto
Period	9/06/19 → 14/06/19

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10.23919/VLSIT.2019.8776513

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Schuddinck, P., Zografos, O., Weckx, P., Matagne, P., Sarkar, S., Sherazi, Y., Baert, R., Jang, D., Yakimets, D., Gupta, A., Parvais, B., Ryckaert, J., Verkest, D., & Mocuta, A. (2019). Device-, Circuit-Block-level evaluation of CFET in a 4 track library. In 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers (pp. T204-T205). Article 8776513 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIT.2019.8776513

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abstract = "The structure of the complementary FET (CFET) with NMOS stacked on top of PMOS, inherently yields standard cells and SRAM cells with 25% smaller layout area, 25% higher pin density and 2x higher routing flexibility than FinFET with same overall active footprint. Moreover, our work, based on advanced modelling, demonstrates that 4 track CFET can match and even outperform 5 track FinFET; without the need to lower S/D contact resistivity down to 5e-10Ωcm2 or to elevate the channel stress up to 2GPa. All gains in power-performance-area at circuit-level are maintained at block-level, making 4 track CFET a suitable candidate for N3 N2 technologies. Keywords: CFET, scaling, S/D engineering, Pi-gate.",

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Schuddinck, P, Zografos, O, Weckx, P, Matagne, P, Sarkar, S, Sherazi, Y, Baert, R, Jang, D, Yakimets, D, Gupta, A, Parvais, B, Ryckaert, J, Verkest, D & Mocuta, A 2019, Device-, Circuit-Block-level evaluation of CFET in a 4 track library. in 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers., 8776513, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2019-June, Institute of Electrical and Electronics Engineers Inc., pp. T204-T205, 39th Symposium on VLSI Technology, VLSI Technology 2019, Kyoto, Japan, 9/06/19. https://doi.org/10.23919/VLSIT.2019.8776513

Device-, Circuit-Block-level evaluation of CFET in a 4 track library. / Schuddinck, P.; Zografos, O.; Weckx, P. et al.
2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. p. T204-T205 8776513 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2019-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference paper

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AU - Matagne, P.

AU - Sarkar, S.

AU - Sherazi, Y.

AU - Baert, R.

AU - Jang, D.

AU - Yakimets, D.

AU - Gupta, A.

AU - Parvais, B.

AU - Ryckaert, J.

AU - Verkest, D.

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AB - The structure of the complementary FET (CFET) with NMOS stacked on top of PMOS, inherently yields standard cells and SRAM cells with 25% smaller layout area, 25% higher pin density and 2x higher routing flexibility than FinFET with same overall active footprint. Moreover, our work, based on advanced modelling, demonstrates that 4 track CFET can match and even outperform 5 track FinFET; without the need to lower S/D contact resistivity down to 5e-10Ωcm2 or to elevate the channel stress up to 2GPa. All gains in power-performance-area at circuit-level are maintained at block-level, making 4 track CFET a suitable candidate for N3 N2 technologies. Keywords: CFET, scaling, S/D engineering, Pi-gate.

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Schuddinck P, Zografos O, Weckx P, Matagne P, Sarkar S, Sherazi Y et al. Device-, Circuit-Block-level evaluation of CFET in a 4 track library. In 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2019. p. T204-T205. 8776513. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.23919/VLSIT.2019.8776513

Device-, Circuit-Block-level evaluation of CFET in a 4 track library

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