3 Citations (Scopus)


We propose a methodology to study and to quantify efficiency and the impact of overheads on runtime performance. Most work on High-Performance Computing (HPC) for FPGAs only studies runtime performance or cost, while we are interested in how far we are from peak performance and, more importantly, why. The efficiency of runtime performance is defined with respect to the ideal computational runtime in absence of inefficiencies. The analysis of the difference between actual and ideal runtime reveals the overheads and bottlenecks. A formal approach is proposed to decompose the efficiency into three components: frequency, area and cycles. After quantification of the efficiencies, a detailed analysis has to reveal the reasons for the lost frequencies, lost area and lost cycles. We propose a taxonomy of possible causes and practical methods to identify and quantify the overheads. The proposed methodology is applied on a number of use cases to illustrate the methodology. We show the interaction between the three components of efficiency and show how bottlenecks are revealed.
Original languageEnglish
Pages (from-to)204-217
Number of pages14
JournalJournal of Parallel and Distributed Computing
Publication statusPublished - Mar 2018


  • FPGA
  • High-Level Synthesis
  • High-Performance Computing
  • Lost cycle analysis
  • Performance efficiency
  • Vivado HLS

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