Efficient Matricization of n-D Array with CUDA and Its Evaluation

Md Abu Hanif Shaikh; K. M.Azharul Hasan; G. G.Md Nawaz Ali; Marwa Chafii; Peter Han Joo Chong

doi:10.1109/CSE-EUC-DCABES.2016.192

Efficient Matricization of n-D Array with CUDA and Its Evaluation

Md Abu Hanif Shaikh, K. M.Azharul Hasan, G. G.Md Nawaz Ali, Marwa Chafii, Peter Han Joo Chong

Research output: Chapter in Book/Report/Conference proceeding › Conference paper

2 Citations (Scopus)

Abstract

Scientific and engineering computing requires operation on flooded amount of data having very high number of dimensions. Traditional multidimensional array is widely popular for implementing higher dimensional data but its' performance diminishes with the increase of the number of dimensions. On the other side, traditional row-column view is facile for implementation, imagination and visualization. This paper details a representation scheme for higher dimensional array with row-column abstraction on parallel environment. Odd dimensions contribute along row-direction and even dimensions along column direction which gives lower cost of index computation, higher data locality and parallelism. Each 2-D block of size blockIdx.x × threadIdx.x is independent of each other. Theoretically, it has no limitation with the number of dimensions and mapping algorithm is unique for any number of dimensions. Performance of the proposed matricization is measured with matrix-matrix addition, subtraction and multiplication operation. Experimental results show promising performance improvement over Traditional Multidimensional Array (TMA) and Extended Karnaugh Map Representation (EKMR). Thus the scheme can be used for implementing higher dimensional array in both general purpose and scientific computing on GPU.

Original language	English
Title of host publication	Proceedings - 19th IEEE International Conference on Computational Science and Engineering, 14th IEEE International Conference on Embedded and Ubiquitous Computing and 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science, CSE-EUC-DCABES 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	246-252
Number of pages	7
ISBN (Electronic)	9781509035939
DOIs	https://doi.org/10.1109/CSE-EUC-DCABES.2016.192
Publication status	Published - 14 Jul 2017
Event	19th IEEE International Conference on Computational Science and Engineering, 14th IEEE International Conference on Embedded and Ubiquitous Computing and 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science, CSE-EUC-DCABES 2016 - Paris, France Duration: 24 Aug 2016 → 26 Aug 2016

Conference

Conference	19th IEEE International Conference on Computational Science and Engineering, 14th IEEE International Conference on Embedded and Ubiquitous Computing and 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science, CSE-EUC-DCABES 2016
Country/Territory	France
City	Paris
Period	24/08/16 → 26/08/16

Keywords

Array operations
CUDA
GPU
High Performance Computing
Matrix Operation
Matrix-Matrix Multiplication
Multidimensional Array
Parallel Computing

Access to Document

10.1109/CSE-EUC-DCABES.2016.192

Cite this

Shaikh, M. A. H., Hasan, K. M. A., Ali, G. G. M. N., Chafii, M., & Chong, P. H. J. (2017). Efficient Matricization of n-D Array with CUDA and Its Evaluation. In Proceedings - 19th IEEE International Conference on Computational Science and Engineering, 14th IEEE International Conference on Embedded and Ubiquitous Computing and 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science, CSE-EUC-DCABES 2016 (pp. 246-252). Article 7982254 Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CSE-EUC-DCABES.2016.192

Shaikh, Md Abu Hanif ; Hasan, K. M.Azharul ; Ali, G. G.Md Nawaz et al. / Efficient Matricization of n-D Array with CUDA and Its Evaluation. Proceedings - 19th IEEE International Conference on Computational Science and Engineering, 14th IEEE International Conference on Embedded and Ubiquitous Computing and 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science, CSE-EUC-DCABES 2016. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 246-252

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abstract = "Scientific and engineering computing requires operation on flooded amount of data having very high number of dimensions. Traditional multidimensional array is widely popular for implementing higher dimensional data but its' performance diminishes with the increase of the number of dimensions. On the other side, traditional row-column view is facile for implementation, imagination and visualization. This paper details a representation scheme for higher dimensional array with row-column abstraction on parallel environment. Odd dimensions contribute along row-direction and even dimensions along column direction which gives lower cost of index computation, higher data locality and parallelism. Each 2-D block of size blockIdx.x × threadIdx.x is independent of each other. Theoretically, it has no limitation with the number of dimensions and mapping algorithm is unique for any number of dimensions. Performance of the proposed matricization is measured with matrix-matrix addition, subtraction and multiplication operation. Experimental results show promising performance improvement over Traditional Multidimensional Array (TMA) and Extended Karnaugh Map Representation (EKMR). Thus the scheme can be used for implementing higher dimensional array in both general purpose and scientific computing on GPU.",

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note = "19th IEEE International Conference on Computational Science and Engineering, 14th IEEE International Conference on Embedded and Ubiquitous Computing and 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science, CSE-EUC-DCABES 2016 ; Conference date: 24-08-2016 Through 26-08-2016",

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Shaikh, MAH, Hasan, KMA, Ali, GGMN, Chafii, M & Chong, PHJ 2017, Efficient Matricization of n-D Array with CUDA and Its Evaluation. in Proceedings - 19th IEEE International Conference on Computational Science and Engineering, 14th IEEE International Conference on Embedded and Ubiquitous Computing and 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science, CSE-EUC-DCABES 2016., 7982254, Institute of Electrical and Electronics Engineers Inc., pp. 246-252, 19th IEEE International Conference on Computational Science and Engineering, 14th IEEE International Conference on Embedded and Ubiquitous Computing and 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science, CSE-EUC-DCABES 2016, Paris, France, 24/08/16. https://doi.org/10.1109/CSE-EUC-DCABES.2016.192

Efficient Matricization of n-D Array with CUDA and Its Evaluation. / Shaikh, Md Abu Hanif; Hasan, K. M.Azharul; Ali, G. G.Md Nawaz et al.
Proceedings - 19th IEEE International Conference on Computational Science and Engineering, 14th IEEE International Conference on Embedded and Ubiquitous Computing and 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science, CSE-EUC-DCABES 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 246-252 7982254.

Research output: Chapter in Book/Report/Conference proceeding › Conference paper

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AU - Shaikh, Md Abu Hanif

AU - Hasan, K. M.Azharul

AU - Ali, G. G.Md Nawaz

AU - Chafii, Marwa

AU - Chong, Peter Han Joo

PY - 2017/7/14

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N2 - Scientific and engineering computing requires operation on flooded amount of data having very high number of dimensions. Traditional multidimensional array is widely popular for implementing higher dimensional data but its' performance diminishes with the increase of the number of dimensions. On the other side, traditional row-column view is facile for implementation, imagination and visualization. This paper details a representation scheme for higher dimensional array with row-column abstraction on parallel environment. Odd dimensions contribute along row-direction and even dimensions along column direction which gives lower cost of index computation, higher data locality and parallelism. Each 2-D block of size blockIdx.x × threadIdx.x is independent of each other. Theoretically, it has no limitation with the number of dimensions and mapping algorithm is unique for any number of dimensions. Performance of the proposed matricization is measured with matrix-matrix addition, subtraction and multiplication operation. Experimental results show promising performance improvement over Traditional Multidimensional Array (TMA) and Extended Karnaugh Map Representation (EKMR). Thus the scheme can be used for implementing higher dimensional array in both general purpose and scientific computing on GPU.

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KW - High Performance Computing

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KW - Matrix-Matrix Multiplication

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BT - Proceedings - 19th IEEE International Conference on Computational Science and Engineering, 14th IEEE International Conference on Embedded and Ubiquitous Computing and 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science, CSE-EUC-DCABES 2016

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Shaikh MAH, Hasan KMA, Ali GGMN, Chafii M, Chong PHJ. Efficient Matricization of n-D Array with CUDA and Its Evaluation. In Proceedings - 19th IEEE International Conference on Computational Science and Engineering, 14th IEEE International Conference on Embedded and Ubiquitous Computing and 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science, CSE-EUC-DCABES 2016. Institute of Electrical and Electronics Engineers Inc. 2017. p. 246-252. 7982254 doi: 10.1109/CSE-EUC-DCABES.2016.192

Efficient Matricization of n-D Array with CUDA and Its Evaluation

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