FAST: an efficient high-level dataflow simulator of mixed-signal front-ends of digital telecom transceivers

Gerd Vandersteen, Piet Wambacq, S. Donnay, Yves Rolain, Wolfgang Eberle

Research output: Chapter in Book/Report/Conference proceedingChapterResearchpeer-review

Abstract

Cost-effective implementations of wireless transceivers must have a small size and a low power consumption. To this purpose the degree of integration should be increased. This requires new front-end architectures and will result into ICs which combine analog and digital circuits. The development of front-end architectures is best supported by simulations at the architectural level. Current methodologies and corresponding tools suffer from common drawbacks, such as lack of accuracy, long simulation times, etc. A new methodology has been developed for efficient simulation, at the architectural level, of mixed-signal front-ends of digital telecom transceivers. The efficient execution is obtained using a local multirate, multicarrier signal respresentation together with a dataflow simulation scheme that dynamically switches to the most efficient signal processing technique available. The methodology has been implemented in the program FAST (Front-end Architecture Simulator for digital Telecom applications).
Original languageEnglish
Title of host publicationChapter in: Low-power design techniques and CAD tools for analog and RF integrated circuits
EditorsP. Wambacq, G. Gielen, J. Gerrits
PublisherKluwer Academic Publishers
Pages43-59
Number of pages17
ISBN (Print)0-7923-7432-0
Publication statusPublished - 1 Jan 2001

Bibliographical note

P. Wambacq, G. Gielen, J. Gerrits

Keywords

  • Front-end Archit. Simulator for digital Telecom

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