Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation

Pratap Renukaswamy; Nereo Markulic; Piet Wambacq; Jan Craninckx

doi:10.1109/ISCAS51556.2021.9401690

Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation

Pratap Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx

Research output: Chapter in Book/Report/Conference proceeding › Conference paper

1 Citation (Scopus)

Abstract

This work extends the concept of feedforward phase noise cancellation (FPNC) technique to a fractional-N subsampling phase-locked loop (SSPLL), using a low-power and low- area ring voltage-controlled oscillator (RVCO). The sub-sampling phase detector is used to measure the RVCO phase noise and its output is used to tune the voltage-controlled delay line (VCDL), in order to cancel the excess phase noise measured. A background calibration algorithm is proposed to calibrate the gain error of the VCDL, which improves the phase noise cancellation accuracy. The system model simulations shows that, the total integrated phase noise of the 2.4 GHz fractional-N SSPLL improves from -20.6 dBc to -34 dBc after phase noise cancellation.

Original language	English
Title of host publication	Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation
Place of Publication	Daegu, Korea
Publisher	Institute of Electrical and Electronics Engineers ( IEEE )
Pages	1-5
ISBN (Electronic)	9781728192017
ISBN (Print)	978-1-7281-9201-7
DOIs	https://doi.org/10.1109/ISCAS51556.2021.9401690
Publication status	Published - 22 May 2021
Event	2021 IEEE International Symposium on Circuits and Systems (ISCAS) - Daegu, Korea, Republic of Duration: 22 May 2021 → 28 May 2021 https://iscas2021.org/

Publication series

Name	2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
ISSN (Print)	0271-4302

Conference

Conference	2021 IEEE International Symposium on Circuits and Systems (ISCAS)
Country	Korea, Republic of
City	Daegu
Period	22/05/21 → 28/05/21
Internet address	https://iscas2021.org/

Bibliographical note

Publisher Copyright:
© 2021 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.

Copyright:
Copyright 2021 Elsevier B.V., All rights reserved.

Access to Document

10.1109/ISCAS51556.2021.9401690

Link to publication in Scopus

Cite this

Renukaswamy, P., Markulic, N., Wambacq, P., & Craninckx, J. (2021). Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. In Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation (pp. 1-5). [9401690] (2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)). Institute of Electrical and Electronics Engineers ( IEEE ). https://doi.org/10.1109/ISCAS51556.2021.9401690

Renukaswamy, Pratap ; Markulic, Nereo ; Wambacq, Piet ; Craninckx, Jan. / Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. Daegu, Korea : Institute of Electrical and Electronics Engineers ( IEEE ), 2021. pp. 1-5 (2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)).

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abstract = "This work extends the concept of feedforward phase noise cancellation (FPNC) technique to a fractional-N subsampling phase-locked loop (SSPLL), using a low-power and low- area ring voltage-controlled oscillator (RVCO). The sub-sampling phase detector is used to measure the RVCO phase noise and its output is used to tune the voltage-controlled delay line (VCDL), in order to cancel the excess phase noise measured. A background calibration algorithm is proposed to calibrate the gain error of the VCDL, which improves the phase noise cancellation accuracy. The system model simulations shows that, the total integrated phase noise of the 2.4 GHz fractional-N SSPLL improves from -20.6 dBc to -34 dBc after phase noise cancellation.",

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Renukaswamy, P, Markulic, N, Wambacq, P & Craninckx, J 2021, Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. in Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation., 9401690, 2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), Institute of Electrical and Electronics Engineers ( IEEE ), Daegu, Korea, pp. 1-5, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, Republic of, 22/05/21. https://doi.org/10.1109/ISCAS51556.2021.9401690

Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. / Renukaswamy, Pratap; Markulic, Nereo; Wambacq, Piet; Craninckx, Jan.

Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. Daegu, Korea : Institute of Electrical and Electronics Engineers ( IEEE ), 2021. p. 1-5 9401690 (2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)).

Research output: Chapter in Book/Report/Conference proceeding › Conference paper

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N2 - This work extends the concept of feedforward phase noise cancellation (FPNC) technique to a fractional-N subsampling phase-locked loop (SSPLL), using a low-power and low- area ring voltage-controlled oscillator (RVCO). The sub-sampling phase detector is used to measure the RVCO phase noise and its output is used to tune the voltage-controlled delay line (VCDL), in order to cancel the excess phase noise measured. A background calibration algorithm is proposed to calibrate the gain error of the VCDL, which improves the phase noise cancellation accuracy. The system model simulations shows that, the total integrated phase noise of the 2.4 GHz fractional-N SSPLL improves from -20.6 dBc to -34 dBc after phase noise cancellation.

AB - This work extends the concept of feedforward phase noise cancellation (FPNC) technique to a fractional-N subsampling phase-locked loop (SSPLL), using a low-power and low- area ring voltage-controlled oscillator (RVCO). The sub-sampling phase detector is used to measure the RVCO phase noise and its output is used to tune the voltage-controlled delay line (VCDL), in order to cancel the excess phase noise measured. A background calibration algorithm is proposed to calibrate the gain error of the VCDL, which improves the phase noise cancellation accuracy. The system model simulations shows that, the total integrated phase noise of the 2.4 GHz fractional-N SSPLL improves from -20.6 dBc to -34 dBc after phase noise cancellation.

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Renukaswamy P, Markulic N, Wambacq P, Craninckx J. Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. In Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. Daegu, Korea: Institute of Electrical and Electronics Engineers ( IEEE ). 2021. p. 1-5. 9401690. (2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)). https://doi.org/10.1109/ISCAS51556.2021.9401690