Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation

Pratap Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx

Research output: Chapter in Book/Report/Conference proceedingConference paper

1 Citation (Scopus)

Abstract

This work extends the concept of feedforward phase noise cancellation (FPNC) technique to a fractional-N subsampling phase-locked loop (SSPLL), using a low-power and low- area ring voltage-controlled oscillator (RVCO). The sub-sampling phase detector is used to measure the RVCO phase noise and its output is used to tune the voltage-controlled delay line (VCDL), in order to cancel the excess phase noise measured. A background calibration algorithm is proposed to calibrate the gain error of the VCDL, which improves the phase noise cancellation accuracy. The system model simulations shows that, the total integrated phase noise of the 2.4 GHz fractional-N SSPLL improves from -20.6 dBc to -34 dBc after phase noise cancellation.
Original languageEnglish
Title of host publicationFractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation
Place of PublicationDaegu, Korea
PublisherInstitute of Electrical and Electronics Engineers ( IEEE )
Pages1-5
ISBN (Electronic)9781728192017
ISBN (Print)978-1-7281-9201-7
DOIs
Publication statusPublished - 22 May 2021
Event2021 IEEE International Symposium on Circuits and Systems (ISCAS) - Daegu, Korea, Republic of
Duration: 22 May 202128 May 2021
https://iscas2021.org/

Publication series

Name2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
ISSN (Print)0271-4302

Conference

Conference2021 IEEE International Symposium on Circuits and Systems (ISCAS)
CountryKorea, Republic of
CityDaegu
Period22/05/2128/05/21
Internet address

Bibliographical note

Publisher Copyright:
© 2021 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.

Copyright:
Copyright 2021 Elsevier B.V., All rights reserved.

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