This work extends the concept of feedforward phase noise cancellation (FPNC) technique to a fractional-N subsampling phase-locked loop (SSPLL), using a low-power and low- area ring voltage-controlled oscillator (RVCO). The sub-sampling phase detector is used to measure the RVCO phase noise and its output is used to tune the voltage-controlled delay line (VCDL), in order to cancel the excess phase noise measured. A background calibration algorithm is proposed to calibrate the gain error of the VCDL, which improves the phase noise cancellation accuracy. The system model simulations shows that, the total integrated phase noise of the 2.4 GHz fractional-N SSPLL improves from -20.6 dBc to -34 dBc after phase noise cancellation.
|Title of host publication||Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation|
|Place of Publication||Daegu, Korea|
|Publisher||Institute of Electrical and Electronics Engineers ( IEEE )|
|Publication status||Published - 22 May 2021|
|Event||2021 IEEE International Symposium on Circuits and Systems (ISCAS) - Daegu, Korea, Republic of|
Duration: 22 May 2021 → 28 May 2021
|Name||2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)|
|Conference||2021 IEEE International Symposium on Circuits and Systems (ISCAS)|
|Country||Korea, Republic of|
|Period||22/05/21 → 28/05/21|
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