High-speed calibrated analog-to-digital converters in CMOS

Analog to digital converters are a key component in many electronic systems. They form the link between the sensitive analog and the robust digital worlds. They are typically designed in CMOS to facilitate integration with the digital part of a larger system. New wireless applications demand high-speed, low resolution analog to digital converters. The converter performance required in these applications was previously only found in a wired context, where the power consumption is not a critical constraint. As a result, the power consumption of existing analog to digital converters would significantly limit the battery lifetime in a wireless application. The goal of this work is to reduce the power consumption of these analog to digital converters through the use of one promising technique in this area: threshold calibration. It is investigated how threshold calibration affects the flash architecture, which is commonly used in this area of the ADC design space. It is shown that calibrated flash converters have lower power consumption and input capacitance than their uncalibrated counterparts. It is also shown that two key trade-offs in uncalibrated converters are equally valid in calibrated converters. Based on these universal trade-offs, two alternative benchmarking metrics are proposed. The reduced input capacitance of calibrated flash converters enables the use of a charge-sharing folding front-end. This front-end can be used to improve the resolution of a given sub-converter by one bit with only a very small power penalty at the cost of increased input capacitance. It is shown that this front-end does not impose a significant speed penalty with respect to a full flash converter. A new architecture enabled by threshold calibration is proposed. By avoiding a linearity requirement for the amplifiers in a pipeline converter, the use of low power high speed amplifiers is enabled. A dynamic amplifier well-suited for this converter is proposed. Using this amplifier, the inherent speed of the architecture is potentially over half that of a full flash converter, with significantly reduced power consumption and input capacitance. The theory in this work is validated through design, implementation and measurement of three prototype analog to digital converters. Each implementation uses a different architecture: flash, folding and pipelined respectively, but all achieve state of the art performance.