Abstract
An 8-phase phase-aligned ring oscillator in 90 nm digital CMOS is presented that operates up to 2 GHz. The low-complexity circuit consumes 13 mW at 2 GHz and 1.2 mW at 400 MHz, while a flat in-band phase noise below -120 dBc/Hz is achieved, in close agreement with the presented theory. The circuit occupies an area of 0.008 mm(2).
| Original language | English |
|---|---|
| Title of host publication | Proceedings of ESSCIRC 2008 |
| Publisher | IEEE |
| Pages | 410-413 |
| Number of pages | 8 |
| ISBN (Electronic) | 978-1-4244-2362-0 |
| ISBN (Print) | 978-1-4244-2361-3 |
| Publication status | Published - 15 Sept 2008 |
| Event | European Solid-State Circuits Conference (ESSCIRC) - Edinburgh, Scotland Duration: 15 Sept 2008 → 19 Sept 2008 http://www.esscirc.org http://www.esscirc2008.org/ |
Other
| Other | European Solid-State Circuits Conference (ESSCIRC) |
|---|---|
| Period | 15/09/08 → 19/09/08 |
| Other | European Solid-State Circuits Conference (ESSCIRC) |
| Internet address |
Keywords
- ring oscillator
- realignment
- Clock multiplier
Projects
- 2 Finished
-
OZR1745: Electronic circuits and devices.
Kuijk, M. (Administrative Promotor)
1/10/07 → 31/12/11
Project: Fundamental
-
OZR1474: Design of high speed CMOS baseband circuits for wireless applications
Kuijk, M. (Administrative Promotor)
1/01/07 → 31/12/08
Project: Applied
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