Low-voltage scaled 6T FinFET SRAM cells

N. Collaert; K. Von Arnim; R. Rooyackers; T. Vandeweyer; A. Mercha; B. Parvais; L. Witters; A. Nackaerts; E. Altamirano Sanchez; M. Demand; A. Hikavyy; S. Demuynck; K. Devriendt; F. Bauer; I. Ferain; A. Veloso; K. De Meyer; S. Biesemans; M. Jurczak

doi:10.1007/978-90-481-9379-0_4

Low-voltage scaled 6T FinFET SRAM cells

N. Collaert, K. Von Arnim, R. Rooyackers, T. Vandeweyer, A. Mercha, B. Parvais, L. Witters, A. Nackaerts, E. Altamirano Sanchez, M. Demand, A. Hikavyy, S. Demuynck, K. Devriendt, F. Bauer, I. Ferain, A. Veloso, K. De Meyer, S. Biesemans, M. Jurczak

Research output: Chapter in Book/Report/Conference proceeding › Conference paper

1 Citation (Scopus)

Abstract

Planar bulk devices suffer from high random dopant fluctuations (RDF) when scaled down to sub-32 nm technology nodes. This is considered as a major roadblock for the integration of these devices in high density 6T SRAM cells [1, 2]. The increasing variation of transistor parameters like V_T, I_ON, I_OFF, etc., can result in a large variability in performance and power. The possibility of leaving the channels undoped and their excellent immunity against Short Channel Effects (SCE) favors the use of FinFET-based multi-gate devices [3] for these technology nodes.

Original language	English
Title of host publication	Emerging Technologies and Circuits
Pages	55-66
Number of pages	12
DOIs	https://doi.org/10.1007/978-90-481-9379-0_4
Publication status	Published - 15 Nov 2010
Event	International Conference on Integrated Circuit Design and Technology, ICICDT 2008 - Grenoble, France Duration: 2 Jun 2008 → 4 Jun 2008

Publication series

Name	Lecture Notes in Electrical Engineering
Volume	2021 LNEE
ISSN (Print)	1876-1100
ISSN (Electronic)	1876-1119

Conference

Conference	International Conference on Integrated Circuit Design and Technology, ICICDT 2008
Country/Territory	France
City	Grenoble
Period	2/06/08 → 4/06/08

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Collaert, N., Von Arnim, K., Rooyackers, R., Vandeweyer, T., Mercha, A., Parvais, B., Witters, L., Nackaerts, A., Sanchez, E. A., Demand, M., Hikavyy, A., Demuynck, S., Devriendt, K., Bauer, F., Ferain, I., Veloso, A., De Meyer, K., Biesemans, S., & Jurczak, M. (2010). Low-voltage scaled 6T FinFET SRAM cells. In Emerging Technologies and Circuits (pp. 55-66). (Lecture Notes in Electrical Engineering; Vol. 2021 LNEE). https://doi.org/10.1007/978-90-481-9379-0_4

@inproceedings{446ccd75e469417faf53b131b46f8960,

title = "Low-voltage scaled 6T FinFET SRAM cells",

abstract = "Planar bulk devices suffer from high random dopant fluctuations (RDF) when scaled down to sub-32 nm technology nodes. This is considered as a major roadblock for the integration of these devices in high density 6T SRAM cells [1, 2]. The increasing variation of transistor parameters like VT, ION, IOFF, etc., can result in a large variability in performance and power. The possibility of leaving the channels undoped and their excellent immunity against Short Channel Effects (SCE) favors the use of FinFET-based multi-gate devices [3] for these technology nodes.",

author = "N. Collaert and {Von Arnim}, K. and R. Rooyackers and T. Vandeweyer and A. Mercha and B. Parvais and L. Witters and A. Nackaerts and Sanchez, {E. Altamirano} and M. Demand and A. Hikavyy and S. Demuynck and K. Devriendt and F. Bauer and I. Ferain and A. Veloso and {De Meyer}, K. and S. Biesemans and M. Jurczak",

year = "2010",

month = nov,

day = "15",

doi = "10.1007/978-90-481-9379-0_4",

language = "English",

isbn = "9789048193783",

series = "Lecture Notes in Electrical Engineering",

pages = "55--66",

booktitle = "Emerging Technologies and Circuits",

note = "International Conference on Integrated Circuit Design and Technology, ICICDT 2008 ; Conference date: 02-06-2008 Through 04-06-2008",

}

Collaert, N, Von Arnim, K, Rooyackers, R, Vandeweyer, T, Mercha, A, Parvais, B, Witters, L, Nackaerts, A, Sanchez, EA, Demand, M, Hikavyy, A, Demuynck, S, Devriendt, K, Bauer, F, Ferain, I, Veloso, A, De Meyer, K, Biesemans, S & Jurczak, M 2010, Low-voltage scaled 6T FinFET SRAM cells. in Emerging Technologies and Circuits. Lecture Notes in Electrical Engineering, vol. 2021 LNEE, pp. 55-66, International Conference on Integrated Circuit Design and Technology, ICICDT 2008, Grenoble, France, 2/06/08. https://doi.org/10.1007/978-90-481-9379-0_4

TY - GEN

T1 - Low-voltage scaled 6T FinFET SRAM cells

AU - Collaert, N.

AU - Von Arnim, K.

AU - Rooyackers, R.

AU - Vandeweyer, T.

AU - Mercha, A.

AU - Parvais, B.

AU - Witters, L.

AU - Nackaerts, A.

AU - Sanchez, E. Altamirano

AU - Demand, M.

AU - Hikavyy, A.

AU - Demuynck, S.

AU - Devriendt, K.

AU - Bauer, F.

AU - Ferain, I.

AU - Veloso, A.

AU - De Meyer, K.

AU - Biesemans, S.

AU - Jurczak, M.

PY - 2010/11/15

Y1 - 2010/11/15

N2 - Planar bulk devices suffer from high random dopant fluctuations (RDF) when scaled down to sub-32 nm technology nodes. This is considered as a major roadblock for the integration of these devices in high density 6T SRAM cells [1, 2]. The increasing variation of transistor parameters like VT, ION, IOFF, etc., can result in a large variability in performance and power. The possibility of leaving the channels undoped and their excellent immunity against Short Channel Effects (SCE) favors the use of FinFET-based multi-gate devices [3] for these technology nodes.

AB - Planar bulk devices suffer from high random dopant fluctuations (RDF) when scaled down to sub-32 nm technology nodes. This is considered as a major roadblock for the integration of these devices in high density 6T SRAM cells [1, 2]. The increasing variation of transistor parameters like VT, ION, IOFF, etc., can result in a large variability in performance and power. The possibility of leaving the channels undoped and their excellent immunity against Short Channel Effects (SCE) favors the use of FinFET-based multi-gate devices [3] for these technology nodes.

UR - http://www.scopus.com/inward/record.url?scp=78651537461&partnerID=8YFLogxK

U2 - 10.1007/978-90-481-9379-0_4

DO - 10.1007/978-90-481-9379-0_4

M3 - Conference paper

AN - SCOPUS:78651537461

SN - 9789048193783

T3 - Lecture Notes in Electrical Engineering

SP - 55

EP - 66

BT - Emerging Technologies and Circuits

T2 - International Conference on Integrated Circuit Design and Technology, ICICDT 2008

Y2 - 2 June 2008 through 4 June 2008

ER -

Low-voltage scaled 6T FinFET SRAM cells

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