Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures

A. Grill, E. Bury, J. Michl, S. Tyaginov, D. Linten, T. Grasser, B. Parvais, B. Kaczer, M. Waltl, I. Radu

Research output: Chapter in Book/Report/Conference proceedingConference paper

6 Citations (Scopus)

Abstract

In this work, we present time-zero variability and degradation data obtained from a large set of on-chip devices in specifically designed arrays, from room temperature to 4K. We show that the investigated nMOS transistors still suffer from significant PBTI and HC degradation down to the lowest temperatures. We further investigate the contribution of multiple-carrier mechanism versus single-carrier mechanism of Si-H bond dissociation across different temperatures. Finally, we extrapolate the time-to-failure for a large gate and drain bias space and show that HCD after on-state stress and off-state stress show opposite temperature trends with the off-state stress being worse at cryogenic temperatures.

Original languageEnglish
Title of host publication2020 IEEE International Reliability Physics Symposium, IRPS 2020 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-6
Number of pages6
ISBN (Electronic)9781728131993
DOIs
Publication statusPublished - Apr 2020
Event2020 IEEE International Reliability Physics Symposium, IRPS 2020 - Virtual, Online, United States
Duration: 28 Apr 202030 May 2020

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
Volume2020-April
ISSN (Print)1541-7026

Conference

Conference2020 IEEE International Reliability Physics Symposium, IRPS 2020
CountryUnited States
CityVirtual, Online
Period28/04/2030/05/20

Keywords

  • 28 nm bulk CMOS
  • 4K
  • Bias Temperature Instability (BTI)
  • Cryoelectronics
  • Cryogenic
  • Degradation Maps
  • Hot Carrier Degradation (HCD)
  • Smart Arrays
  • Variability

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