Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling

A. Vandooren, L. Witters, J. Franco, A. Mallik, B. Parvais, Z. Wu, A. Walke, V. Deshpande, E. Rosseel, A. Hikavyy, W. Li, L. Peng, N. Rassoul, G. Jamieson, F. Inoue, G. Verbinnen, K. Devriendt, L. Teugels, N. Heylen, E. VecchioT. Zheng, N. Waldron, V. De Heyn, D. Mocuta, N. Collaert

Research output: Chapter in Book/Report/Conference proceedingConference paper

4 Citations (Scopus)

Abstract

In this paper, we review the current progress on 3D sequential device stacking, highlighting the main integration challenges and the possible technological solutions. Next, we explore the potential benefits of 3D sequential stacking at transistor level, CMOS level and for hybrid circuits.

Original languageEnglish
Title of host publicationICICDT 2018 - International Conference on IC Design and Technology, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages145-148
Number of pages4
ISBN (Electronic)9781538625491
ISBN (Print)9781538625491
DOIs
Publication statusPublished - 27 Jun 2018
Event2018 International Conference on IC Design and Technology, ICICDT 2018 - Otranto, Italy
Duration: 4 Jun 20186 Jun 2018

Publication series

NameICICDT 2018 - International Conference on IC Design and Technology, Proceedings

Conference

Conference2018 International Conference on IC Design and Technology, ICICDT 2018
CountryItaly
CityOtranto
Period4/06/186/06/18

Keywords

  • 3D sequential
  • junctionless
  • silicon-on-insulator
  • thermal budget
  • wafer bonding

Fingerprint Dive into the research topics of 'Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling'. Together they form a unique fingerprint.

Cite this