Architectural study of reconfigurable photonicNetworks on chip (NoC)

  • Mikel Loperena Lopez ((PhD) Student)
  • Hugo Thienpont (Promotor)
  • Christof Debaes (Co-promotor)
  • Inigo Artundo Martinez (Jury)

Student thesis: Master's Thesis


In this master thesis we have done a performance study, of reconfigurable photonic Network-on-Chip (NoC) for multiprocessor and multicore Systems-on-Chip (SoCs) with a special focus on power consumption. Driven by recent advances in silicon photonics technology, we believe it will be possible to integrate photonic communication channels on future highly multicore processors chips. Although several proposals of photonic NoC exist in scientific literature, a long set-up time of the photonic channel is currently always limiting the use of the network to the communication of large data packets (>~1kByte). We blieve that we are the first to propose a solution which amortizes this set-up delay by providing the photonic channels as short-cuts to an underlying packet-switched network with fixed topology. Our solution can therefore be directly applied to the shared memory model of current Chip Multi-Processors (CMPs).
The opportunity of the reconfigurable capabilities spring from the fact that communication in multiprocessor systems tends to follow certain patterns with outspoken traffic bursts. In our solution, at each reconfiguration interval, the most communicating partners will have a photonic shortcut at their disposal which both reduce latency and the congestion of the network.
To test the performance of our proposed netword, we ran several different parallel benchmark applications in a full system execution driven simulator, called Simics. The simulator was furthermore extended with the necessary modules to simulate the interprocessor network accurately developed earlier in a collaboration with the ELIS group of the Ghent University. We developed furthermore the required tools that where necessary to estimate the power of the switches in the photonic links.
After collecting all the data, we can conclude that our approach presents significant better average memory access latency performance (35% to 42% reduction) than a comparable ficed network with onl a modest power consumption penalty (18% to 51% increase). The proposal is nevertheless consuming significantly lower power than a high-speed fixed electrical or optical network (18% to 63% reduction). As such, we can conclude that our proposal seems to be a good trade-off between network performance and power consumption.
Date of Award2009
Original languageEnglish
SupervisorHugo Thienpont (Promotor), Christof Debaes (Co-promotor) & Inigo Artundo Martinez (Jury)


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