3D technologies for analog/RF applications

A. Vandooren; B. Parvais; L. Witters; A. Walke; A. Vais; C. Merckling; D. Lin; N. Waldron; P. Wambacq; D. Mocuta; N. Collaert

doi:10.1109/S3S.2017.8308746

3D technologies for analog/RF applications

A. Vandooren, B. Parvais, L. Witters, A. Walke, A. Vais, C. Merckling, D. Lin, N. Waldron, P. Wambacq, D. Mocuta, N. Collaert

Onderzoeksoutput: Conference paper

3 Citaten (Scopus)

Samenvatting

In this work, we will review possible technology options for next generation wireless communication. Next to the introduction of specific device architectures and materials, dissimilar from standard Si CMOS, the challenge will lie in the co-integration of these non-Si technologies with CMOS to enable power efficient systems with high performance, in this case high speed and output power, and reduced form factor. Next to monolithic integration, sequential 3D, currently been investigated for LOGIC density scaling, can be one of the enablers, allowing to combine technologies with very different needs at a finer grain and thus higher density than traditional 3D-SOC and 3D-IC technologies.

Originele taal-2	English
Titel	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Uitgeverij	Institute of Electrical and Electronics Engineers Inc.
Pagina's	1-3
Aantal pagina's	3
Volume	2018-March
ISBN van elektronische versie	9781538637654
ISBN van geprinte versie	9781538637654
DOI's	https://doi.org/10.1109/S3S.2017.8308746
Status	Published - 7 mrt 2018
Evenement	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 - Burlingame, United States Duur: 16 okt 2017 → 18 okt 2017

Publicatie series

Naam	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Volume	2018-March

Conference

Conference	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Land	United States
Stad	Burlingame
Periode	16/10/17 → 18/10/17

Toegang tot document

10.1109/S3S.2017.8308746

Link to publication in Scopus

1 Actief

SRP19: Centrum voor modelgebaseerde systeemverbetering - van computer-gerichte engineering tot model-gerichte engineering
Vandersteen, G., Rolain, Y., Wambacq, P., Kuijk, M., Vandersteen, G., Rolain, Y., Wambacq, P. & Kuijk, M.
1/11/12 → 31/10/24
Project: Fundamenteel

Citeer dit

Vandooren, A., Parvais, B., Witters, L., Walke, A., Vais, A., Merckling, C., Lin, D., Waldron, N., Wambacq, P., Mocuta, D., & Collaert, N. (2018). 3D technologies for analog/RF applications. In 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 (Vol. 2018-March, blz. 1-3). (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017; Vol. 2018-March). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/S3S.2017.8308746

Vandooren, A. ; Parvais, B. ; Witters, L. ; Walke, A. ; Vais, A. ; Merckling, C. ; Lin, D. ; Waldron, N. ; Wambacq, P. ; Mocuta, D. ; Collaert, N. / 3D technologies for analog/RF applications. 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Vol. 2018-March Institute of Electrical and Electronics Engineers Inc., 2018. blz. 1-3 (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017).

@inproceedings{a09cf9bb729540558dbbbd409274d48b,

title = "3D technologies for analog/RF applications",

abstract = "In this work, we will review possible technology options for next generation wireless communication. Next to the introduction of specific device architectures and materials, dissimilar from standard Si CMOS, the challenge will lie in the co-integration of these non-Si technologies with CMOS to enable power efficient systems with high performance, in this case high speed and output power, and reduced form factor. Next to monolithic integration, sequential 3D, currently been investigated for LOGIC density scaling, can be one of the enablers, allowing to combine technologies with very different needs at a finer grain and thus higher density than traditional 3D-SOC and 3D-IC technologies.",

keywords = "III-V, monolithic integration, sequential 3D",

author = "A. Vandooren and B. Parvais and L. Witters and A. Walke and A. Vais and C. Merckling and D. Lin and N. Waldron and P. Wambacq and D. Mocuta and N. Collaert",

year = "2018",

month = mar,

day = "7",

doi = "10.1109/S3S.2017.8308746",

language = "English",

isbn = "9781538637654",

volume = "2018-March",

series = "2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1--3",

booktitle = "2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017",

address = "United States",

note = "2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 ; Conference date: 16-10-2017 Through 18-10-2017",

}

Vandooren, A, Parvais, B, Witters, L, Walke, A, Vais, A, Merckling, C, Lin, D, Waldron, N, Wambacq, P, Mocuta, D & Collaert, N 2018, 3D technologies for analog/RF applications. in 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. vol. 2018-March, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, vol. 2018-March, Institute of Electrical and Electronics Engineers Inc., blz. 1-3, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Burlingame, United States, 16/10/17. https://doi.org/10.1109/S3S.2017.8308746

3D technologies for analog/RF applications. / Vandooren, A.; Parvais, B.; Witters, L.; Walke, A.; Vais, A.; Merckling, C.; Lin, D.; Waldron, N.; Wambacq, P.; Mocuta, D.; Collaert, N.

2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Vol. 2018-March Institute of Electrical and Electronics Engineers Inc., 2018. blz. 1-3 (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017; Vol. 2018-March).

Onderzoeksoutput: Conference paper

TY - GEN

T1 - 3D technologies for analog/RF applications

AU - Vandooren, A.

AU - Parvais, B.

AU - Witters, L.

AU - Walke, A.

AU - Vais, A.

AU - Merckling, C.

AU - Lin, D.

AU - Waldron, N.

AU - Wambacq, P.

AU - Mocuta, D.

AU - Collaert, N.

PY - 2018/3/7

Y1 - 2018/3/7

N2 - In this work, we will review possible technology options for next generation wireless communication. Next to the introduction of specific device architectures and materials, dissimilar from standard Si CMOS, the challenge will lie in the co-integration of these non-Si technologies with CMOS to enable power efficient systems with high performance, in this case high speed and output power, and reduced form factor. Next to monolithic integration, sequential 3D, currently been investigated for LOGIC density scaling, can be one of the enablers, allowing to combine technologies with very different needs at a finer grain and thus higher density than traditional 3D-SOC and 3D-IC technologies.

AB - In this work, we will review possible technology options for next generation wireless communication. Next to the introduction of specific device architectures and materials, dissimilar from standard Si CMOS, the challenge will lie in the co-integration of these non-Si technologies with CMOS to enable power efficient systems with high performance, in this case high speed and output power, and reduced form factor. Next to monolithic integration, sequential 3D, currently been investigated for LOGIC density scaling, can be one of the enablers, allowing to combine technologies with very different needs at a finer grain and thus higher density than traditional 3D-SOC and 3D-IC technologies.

KW - III-V

KW - monolithic integration

KW - sequential 3D

UR - http://www.scopus.com/inward/record.url?scp=85047780033&partnerID=8YFLogxK

U2 - 10.1109/S3S.2017.8308746

DO - 10.1109/S3S.2017.8308746

M3 - Conference paper

AN - SCOPUS:85047780033

SN - 9781538637654

VL - 2018-March

T3 - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

SP - 1

EP - 3

BT - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

Y2 - 16 October 2017 through 18 October 2017

ER -

Vandooren A, Parvais B, Witters L, Walke A, Vais A, Merckling C et al. 3D technologies for analog/RF applications. In 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Vol. 2018-March. Institute of Electrical and Electronics Engineers Inc. 2018. blz. 1-3. (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017). https://doi.org/10.1109/S3S.2017.8308746

3D technologies for analog/RF applications

Samenvatting

Publicatie series

Conference

Toegang tot document

Vingerafdruk

Projecten

SRP19: Centrum voor modelgebaseerde systeemverbetering - van computer-gerichte engineering tot model-gerichte engineering

Citeer dit