A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers

Jorge Luis Lagos Benites, Benjamin Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx

Onderzoeksoutput: Article

13 Citaten (Scopus)

Samenvatting

Ring amplification has recently been shown capable of simultaneously achieving high linearity and high bandwidth (BW) in low-voltage, deep nanoscale CMOS processes, while retaining good power efficiency. In these processes, the low but very flat open-loop (OL) gain versus output voltage characteristic of the ring amplifier can be exploited, together with its high BW, to overcome the low intrinsic gain limitations that otherwise mandate the use of power-consuming analog circuits and complex digital calibration. Within this context, this paper introduces the techniques of dead-zone degeneration (DZD) and second-stage bias enhancement to further extend the linearity and speed limits of the ring amplifier, respectively. These techniques are applied to a 12-b, 1-GS/s, single-channel pipelined ADC implemented in a 28-nm planar CMOS process, which achieves 56.6-dB SNDR and 73.1-dB SFDR while consuming 24.8 mW from a single 0.9-V supply, resulting in Schreier and Walden figure-of-merit (FoM) values of 159.6 dB and 45 fJ/conv.-step, respectively.
Originele taal-2English
Artikelnummer8618444
Pagina's (van-tot)646-658
Aantal pagina's13
TijdschriftIEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume54
Nummer van het tijdschrift3
DOI's
StatusPublished - 18 jan 2019

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