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A 10-GHz sub-sampling phase-locked loop (PLL) (SSPLL) with wideband low-noise frequency modulation for frequency-modulated continuous-wave (FMCW) radar applications is presented. It uses a low-power charge-integrating digital-to-analog converter (QDAC) to tune the voltage-controlled oscillator (VCO) in a two-point modulation architecture. A full background calibration engine corrects for the nonlinearities in the QDAC modulation path. Implemented in a 28-nm CMOS process, the SSPLL consumes 11.7 mW (of which less-than 0.5 mW from the QDAC) to generate a 23.6-MHz/µs sawtooth chirp-slope with 28-kHz rms-frequency-error for 1.21-GHz chirp-bandwidth.
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Manuscript received April 24, 2020; revised June 27, 2020 and August 20, 2020; accepted August 25, 2020. Date of publication September 15, 2020; date of current version November 24, 2020. This article was approved by Associate Editor Jaehyouk Choi. This work was supported by the European Community’s ECSEL Joint Undertaking through the Grant 783190 - Project PRYSTINE. (Corresponding author: Pratap Tumkur Renukaswamy.) Pratap Tumkur Renukaswamy and Piet Wambacq are with imec, 3001 Leu-ven, Belgium, and also with the Department ETRO, Vrije Universiteit Brussel, 1050 Brussels, Belgium (e-mail: firstname.lastname@example.org; email@example.com).
This work was supported by the European Community's ECSEL Joint Undertaking through the Grant 783190 - Project PRYSTINE.
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- 7 Citaties
- 1 Conference paper
A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp BandwidthRenukaswamy, P., Markulic, N., Park, S., Kankuppe Raghavendra Swamy, A., Shi, Q., Wambacq, P. & Craninckx, J., 18 feb 2020, 2020 International Solid-State Circuits Conference. San Francisco: Institute of Electrical and Electronics Engineers ( IEEE ), blz. 278-280 3 blz. 17.7
Onderzoeksoutput: Conference paper13 Citaten (Scopus)