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A 10-GHz sub-sampling phase-locked loop (PLL) (SSPLL) with wideband low-noise frequency modulation for frequency-modulated continuous-wave (FMCW) radar applications is presented. It uses a low-power charge-integrating digital-to-analog converter (QDAC) to tune the voltage-controlled oscillator (VCO) in a two-point modulation architecture. A full background calibration engine corrects for the nonlinearities in the QDAC modulation path. Implemented in a 28-nm CMOS process, the SSPLL consumes 11.7 mW (of which less-than 0.5 mW from the QDAC) to generate a 23.6-MHz/µs sawtooth chirp-slope with 28-kHz rms-frequency-error for 1.21-GHz chirp-bandwidth.
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- 1 Conference paper
A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp BandwidthRenukaswamy, P., Markulic, N., Park, S., Kankuppe Raghavendra Swamy, A., Shi, Q., Wambacq, P. & Craninckx, J., 18 feb 2020, 2020 International Solid-State Circuits Conference. San Francisco: Institute of Electrical and Electronics Engineers ( IEEE ), blz. 278-280 3 blz. 17.7
Onderzoeksoutput: Conference paper6 Citaten (Scopus)