A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth

Pratap Renukaswamy; Nereo Markulic; Piet Wambacq; Jan Craninckx

doi:10.1109/JSSC.2020.3021311

A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth

Pratap Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx

Onderzoeksoutput: Article › peer review

7 Citaten (Scopus)

Samenvatting

A 10-GHz sub-sampling phase-locked loop (PLL) (SSPLL) with wideband low-noise frequency modulation for frequency-modulated continuous-wave (FMCW) radar applications is presented. It uses a low-power charge-integrating digital-to-analog converter (QDAC) to tune the voltage-controlled oscillator (VCO) in a two-point modulation architecture. A full background calibration engine corrects for the nonlinearities in the QDAC modulation path. Implemented in a 28-nm CMOS process, the SSPLL consumes 11.7 mW (of which less-than 0.5 mW from the QDAC) to generate a 23.6-MHz/µs sawtooth chirp-slope with 28-kHz rms-frequency-error for 1.21-GHz chirp-bandwidth.

Originele taal-2	English
Artikelnummer	9197684
Pagina's (van-tot)	3294-3307
Aantal pagina's	14
Tijdschrift	IEEE Journal of Solid - State Circuits
Volume	55
Nummer van het tijdschrift	12
DOI's	https://doi.org/10.1109/JSSC.2020.3021311
Status	Published - 15 sep 2020

Bibliografische nota

Funding Information:
Manuscript received April 24, 2020; revised June 27, 2020 and August 20, 2020; accepted August 25, 2020. Date of publication September 15, 2020; date of current version November 24, 2020. This article was approved by Associate Editor Jaehyouk Choi. This work was supported by the European Community’s ECSEL Joint Undertaking through the Grant 783190 - Project PRYSTINE. (Corresponding author: Pratap Tumkur Renukaswamy.) Pratap Tumkur Renukaswamy and Piet Wambacq are with imec, 3001 Leu-ven, Belgium, and also with the Department ETRO, Vrije Universiteit Brussel, 1050 Brussels, Belgium (e-mail: pratap.renukaswamy@imec.be; piet.wambacq@imec.be).

Funding Information:
This work was supported by the European Community's ECSEL Joint Undertaking through the Grant 783190 - Project PRYSTINE.

Publisher Copyright:
© 1966-2012 IEEE.

Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.

Toegang tot document

10.1109/JSSC.2020.3021311Licentie: Unspecified

Link to publication in Scopus

1 Actief

SRP19: Centrum voor modelgebaseerde systeemverbetering - van computer-gerichte engineering tot model-gerichte engineering
Vandersteen, G., Rolain, Y., Wambacq, P., Kuijk, M., Vandersteen, G., Rolain, Y., Wambacq, P. & Kuijk, M.
1/11/12 → 31/10/24
Project: Fundamenteel

7 Citaties
1 Conference paper

A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp Bandwidth
Renukaswamy, P., Markulic, N., Park, S., Kankuppe Raghavendra Swamy, A., Shi, Q., Wambacq, P. & Craninckx, J., 18 feb 2020, 2020 International Solid-State Circuits Conference. San Francisco: Institute of Electrical and Electronics Engineers ( IEEE ), blz. 278-280 3 blz. 17.7
Onderzoeksoutput: Conference paper

13 Citaten (Scopus)

Citeer dit

@article{07870bb4a8994f7cbb658070e7a1cdfa,

title = "A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth",

abstract = "A 10-GHz sub-sampling phase-locked loop (PLL) (SSPLL) with wideband low-noise frequency modulation for frequency-modulated continuous-wave (FMCW) radar applications is presented. It uses a low-power charge-integrating digital-to-analog converter (QDAC) to tune the voltage-controlled oscillator (VCO) in a two-point modulation architecture. A full background calibration engine corrects for the nonlinearities in the QDAC modulation path. Implemented in a 28-nm CMOS process, the SSPLL consumes 11.7 mW (of which less-than 0.5 mW from the QDAC) to generate a 23.6-MHz/µs sawtooth chirp-slope with 28-kHz rms-frequency-error for 1.21-GHz chirp-bandwidth.",

author = "Pratap Renukaswamy and Nereo Markulic and Piet Wambacq and Jan Craninckx",

note = "Funding Information: Manuscript received April 24, 2020; revised June 27, 2020 and August 20, 2020; accepted August 25, 2020. Date of publication September 15, 2020; date of current version November 24, 2020. This article was approved by Associate Editor Jaehyouk Choi. This work was supported by the European Community{\textquoteright}s ECSEL Joint Undertaking through the Grant 783190 - Project PRYSTINE. (Corresponding author: Pratap Tumkur Renukaswamy.) Pratap Tumkur Renukaswamy and Piet Wambacq are with imec, 3001 Leu-ven, Belgium, and also with the Department ETRO, Vrije Universiteit Brussel, 1050 Brussels, Belgium (e-mail: pratap.renukaswamy@imec.be; piet.wambacq@imec.be). Funding Information: This work was supported by the European Community's ECSEL Joint Undertaking through the Grant 783190 - Project PRYSTINE. Publisher Copyright: {\textcopyright} 1966-2012 IEEE. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.",

year = "2020",

month = sep,

day = "15",

doi = "10.1109/JSSC.2020.3021311",

language = "English",

volume = "55",

pages = "3294--3307",

journal = "IEEE JOURNAL OF SOLID-STATE CIRCUITS",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "12",

}

TY - JOUR

T1 - A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth

AU - Renukaswamy, Pratap

AU - Markulic, Nereo

AU - Wambacq, Piet

AU - Craninckx, Jan

N1 - Funding Information: Manuscript received April 24, 2020; revised June 27, 2020 and August 20, 2020; accepted August 25, 2020. Date of publication September 15, 2020; date of current version November 24, 2020. This article was approved by Associate Editor Jaehyouk Choi. This work was supported by the European Community’s ECSEL Joint Undertaking through the Grant 783190 - Project PRYSTINE. (Corresponding author: Pratap Tumkur Renukaswamy.) Pratap Tumkur Renukaswamy and Piet Wambacq are with imec, 3001 Leu-ven, Belgium, and also with the Department ETRO, Vrije Universiteit Brussel, 1050 Brussels, Belgium (e-mail: pratap.renukaswamy@imec.be; piet.wambacq@imec.be). Funding Information: This work was supported by the European Community's ECSEL Joint Undertaking through the Grant 783190 - Project PRYSTINE. Publisher Copyright: © 1966-2012 IEEE. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.

PY - 2020/9/15

Y1 - 2020/9/15

N2 - A 10-GHz sub-sampling phase-locked loop (PLL) (SSPLL) with wideband low-noise frequency modulation for frequency-modulated continuous-wave (FMCW) radar applications is presented. It uses a low-power charge-integrating digital-to-analog converter (QDAC) to tune the voltage-controlled oscillator (VCO) in a two-point modulation architecture. A full background calibration engine corrects for the nonlinearities in the QDAC modulation path. Implemented in a 28-nm CMOS process, the SSPLL consumes 11.7 mW (of which less-than 0.5 mW from the QDAC) to generate a 23.6-MHz/µs sawtooth chirp-slope with 28-kHz rms-frequency-error for 1.21-GHz chirp-bandwidth.

AB - A 10-GHz sub-sampling phase-locked loop (PLL) (SSPLL) with wideband low-noise frequency modulation for frequency-modulated continuous-wave (FMCW) radar applications is presented. It uses a low-power charge-integrating digital-to-analog converter (QDAC) to tune the voltage-controlled oscillator (VCO) in a two-point modulation architecture. A full background calibration engine corrects for the nonlinearities in the QDAC modulation path. Implemented in a 28-nm CMOS process, the SSPLL consumes 11.7 mW (of which less-than 0.5 mW from the QDAC) to generate a 23.6-MHz/µs sawtooth chirp-slope with 28-kHz rms-frequency-error for 1.21-GHz chirp-bandwidth.

UR - http://www.scopus.com/inward/record.url?scp=85097238772&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2020.3021311

DO - 10.1109/JSSC.2020.3021311

M3 - Article

VL - 55

SP - 3294

EP - 3307

JO - IEEE JOURNAL OF SOLID-STATE CIRCUITS

JF - IEEE JOURNAL OF SOLID-STATE CIRCUITS

SN - 0018-9200

IS - 12

M1 - 9197684

ER -

A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth

Samenvatting

Bibliografische nota

Toegang tot document

Projecten

SRP19: Centrum voor modelgebaseerde systeemverbetering - van computer-gerichte engineering tot model-gerichte engineering

Onderzoekersoutput

A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp Bandwidth

Citeer dit