A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth

Pratap Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx

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1 Citaat (Scopus)


A 10-GHz sub-sampling phase-locked loop (PLL) (SSPLL) with wideband low-noise frequency modulation for frequency-modulated continuous-wave (FMCW) radar applications is presented. It uses a low-power charge-integrating digital-to-analog converter (QDAC) to tune the voltage-controlled oscillator (VCO) in a two-point modulation architecture. A full background calibration engine corrects for the nonlinearities in the QDAC modulation path. Implemented in a 28-nm CMOS process, the SSPLL consumes 11.7 mW (of which less-than 0.5 mW from the QDAC) to generate a 23.6-MHz/µs sawtooth chirp-slope with 28-kHz rms-frequency-error for 1.21-GHz chirp-bandwidth.
Originele taal-2English
Pagina's (van-tot)3294-3307
Aantal pagina's14
TijdschriftIEEE Journal of Solid - State Circuits
Nummer van het tijdschrift12
StatusPublished - 15 sep 2020

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