A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth

Pratap Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx

Onderzoeksoutput: Articlepeer review

7 Citaten (Scopus)


A 10-GHz sub-sampling phase-locked loop (PLL) (SSPLL) with wideband low-noise frequency modulation for frequency-modulated continuous-wave (FMCW) radar applications is presented. It uses a low-power charge-integrating digital-to-analog converter (QDAC) to tune the voltage-controlled oscillator (VCO) in a two-point modulation architecture. A full background calibration engine corrects for the nonlinearities in the QDAC modulation path. Implemented in a 28-nm CMOS process, the SSPLL consumes 11.7 mW (of which less-than 0.5 mW from the QDAC) to generate a 23.6-MHz/µs sawtooth chirp-slope with 28-kHz rms-frequency-error for 1.21-GHz chirp-bandwidth.
Originele taal-2English
Pagina's (van-tot)3294-3307
Aantal pagina's14
TijdschriftIEEE Journal of Solid - State Circuits
Nummer van het tijdschrift12
StatusPublished - 15 sep 2020

Bibliografische nota

Funding Information:
Manuscript received April 24, 2020; revised June 27, 2020 and August 20, 2020; accepted August 25, 2020. Date of publication September 15, 2020; date of current version November 24, 2020. This article was approved by Associate Editor Jaehyouk Choi. This work was supported by the European Community’s ECSEL Joint Undertaking through the Grant 783190 - Project PRYSTINE. (Corresponding author: Pratap Tumkur Renukaswamy.) Pratap Tumkur Renukaswamy and Piet Wambacq are with imec, 3001 Leu-ven, Belgium, and also with the Department ETRO, Vrije Universiteit Brussel, 1050 Brussels, Belgium (e-mail: pratap.renukaswamy@imec.be; piet.wambacq@imec.be).

Funding Information:
This work was supported by the European Community's ECSEL Joint Undertaking through the Grant 783190 - Project PRYSTINE.

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