A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth

Pratap Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx

Onderzoeksoutput: Article › peer review

7 Citaten (Scopus)

7 Citaties
1 Conference paper

1 resultaten

2020

A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp Bandwidth
Renukaswamy, P., Markulic, N., Park, S., Kankuppe Raghavendra Swamy, A., Shi, Q., Wambacq, P. & Craninckx, J., 18 feb 2020, 2020 International Solid-State Circuits Conference. San Francisco: Institute of Electrical and Electronics Engineers ( IEEE ), blz. 278-280 3 blz. 17.7
Onderzoeksoutput: Conference paper

13 Citaten (Scopus)