A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp Bandwidth

Onderzoeksoutput: Conference paper

6 Citaten (Scopus)

Samenvatting

A 10GHz FMCW subsampling PLL is presented, that uses a low-power charge-integrating QDAC to tune the VCO for wideband low-noise modulation. Nonlinearities in the QDAC modulation path are corrected within 700µsec cold start-up, followed by a full on-chip background calibration engine to track supply and temperature variations. The PLL consumes 11.7mW (of which <0.5mW in the QDAC) to generate a 23.6MHz/µs chirp slope with 89kHz rms-frequency-error for 1.21GHz chirp-bandwidth.
Originele taal-2English
Titel2020 International Solid-State Circuits Conference
Plaats van productieSan Francisco
UitgeverijInstitute of Electrical and Electronics Engineers ( IEEE )
Hoofdstuk17
Pagina's278-280
Aantal pagina's3
DOI's
StatusPublished - 18 feb 2020
Evenement2020 International Solid-State Circuits Conference: Frequency Synthesizers & VCOs - SAN FRANCISCO MARRIOTT MARQUIS HOTEL, SAN FRANCISCO, Belgium
Duur: 16 feb 202020 feb 2020
Congresnummer: 17
http://submissions2.mirasmart.com/ISSCC2020/PDF/ISSCC2020AdvanceProgram.pdf

Conference

Conference2020 International Solid-State Circuits Conference
Verkorte titelISSCC 2020
LandBelgium
StadSAN FRANCISCO
Periode16/02/2020/02/20
Internet adres

Keywords

  • PLL
  • FMCW radar
  • Sub-sampling PLL
  • Integrating DAC
  • Background calibration

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