A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter

Cheng Hsueh Tsai, Federico Pepe, Giovanni Mangraviti, Zhiwei Zong, Jan Craninckx, Piet Wambacq

Onderzoeksoutput: Conference paper

1 Citaat (Scopus)

Samenvatting

We present a 22.5-27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for mm-wave communication. The fast lock is achieved with the help of the proposed gear-shift algorithm,scaling up the PLL bandwidth for faster settling,and orderly reducing it for jitter performance. A digitally controlled oscillator (DCO),based on transformer feedback with a tunable source-bridged capacitor,exhibits low phase noise (PN) over a wide tuning range (FoM of -184 dBc/Hz and FoMT of -191 dBc/Hz). The PLL occupies 0.09-mm2 core area and exhibits 220-fs RMS jitter while consuming 25 mW,giving FoMRMS of -239 dB. Its settling time improves from 780 to 45 μs with our gear-shift algorithm. For 60-GHz communication,with a frequency multiplication factor of 2.5,this PLL covers all six channel frequencies of IEEE-802.11ad and is capable of supporting 128 QAM and beyond.

Originele taal-2English
TitelESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference
UitgeverijInstitute of Electrical and Electronics Engineers Inc.
Pagina's111-114
Aantal pagina's4
ISBN van elektronische versie9781728115504
DOI's
StatusPublished - 1 sep 2019
Evenement45th IEEE European Solid State Circuits Conference, ESSCIRC 2019 - Cracow, Poland
Duur: 23 sep 201926 sep 2019

Publicatie series

NaamESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference

Conference

Conference45th IEEE European Solid State Circuits Conference, ESSCIRC 2019
LandPoland
StadCracow
Periode23/09/1926/09/19

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