A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter

Cheng Hsueh Tsai; Federico Pepe; Giovanni Mangraviti; Zhiwei Zong; Jan Craninckx; Piet Wambacq

doi:10.1109/ESSCIRC.2019.8902868

A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter

Cheng Hsueh Tsai, Federico Pepe, Giovanni Mangraviti, Zhiwei Zong, Jan Craninckx, Piet Wambacq

Onderzoeksoutput: Conference paper

1 Citaat (Scopus)

Samenvatting

We present a 22.5-27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for mm-wave communication. The fast lock is achieved with the help of the proposed gear-shift algorithm,scaling up the PLL bandwidth for faster settling,and orderly reducing it for jitter performance. A digitally controlled oscillator (DCO),based on transformer feedback with a tunable source-bridged capacitor,exhibits low phase noise (PN) over a wide tuning range (FoM of -184 dBc/Hz and FoM_T of -191 dBc/Hz). The PLL occupies 0.09-mm² core area and exhibits 220-fs RMS jitter while consuming 25 mW,giving FoMRMS of -239 dB. Its settling time improves from 780 to 45 μs with our gear-shift algorithm. For 60-GHz communication,with a frequency multiplication factor of 2.5,this PLL covers all six channel frequencies of IEEE-802.11ad and is capable of supporting 128 QAM and beyond.

Originele taal-2	English
Titel	ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference
Uitgeverij	Institute of Electrical and Electronics Engineers Inc.
Pagina's	111-114
Aantal pagina's	4
ISBN van elektronische versie	9781728115504
DOI's	https://doi.org/10.1109/ESSCIRC.2019.8902868
Status	Published - 1 sep 2019
Evenement	45th IEEE European Solid State Circuits Conference, ESSCIRC 2019 - Cracow, Poland Duur: 23 sep 2019 → 26 sep 2019

Publicatie series

Naam	ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference

Conference

Conference	45th IEEE European Solid State Circuits Conference, ESSCIRC 2019
Land	Poland
Stad	Cracow
Periode	23/09/19 → 26/09/19

Toegang tot document

10.1109/ESSCIRC.2019.8902868

Link to publication in Scopus

1 Actief

SRP19: Centrum voor modelgebaseerde systeemverbetering - van computer-gerichte engineering tot model-gerichte engineering
Vandersteen, G., Rolain, Y., Wambacq, P., Kuijk, M., Vandersteen, G., Rolain, Y., Wambacq, P. & Kuijk, M.
1/11/12 → 31/10/24
Project: Fundamenteel

Citeer dit

Tsai, C. H., Pepe, F., Mangraviti, G., Zong, Z., Craninckx, J., & Wambacq, P. (2019). A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter. In ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (blz. 111-114). [8902868] (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ESSCIRC.2019.8902868

Tsai, Cheng Hsueh ; Pepe, Federico ; Mangraviti, Giovanni ; Zong, Zhiwei ; Craninckx, Jan ; Wambacq, Piet. / A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter. ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2019. blz. 111-114 (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference).

@inproceedings{92837a21d76f4350ae631d1df5b68cbe,

title = "A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter",

abstract = "We present a 22.5-27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for mm-wave communication. The fast lock is achieved with the help of the proposed gear-shift algorithm,scaling up the PLL bandwidth for faster settling,and orderly reducing it for jitter performance. A digitally controlled oscillator (DCO),based on transformer feedback with a tunable source-bridged capacitor,exhibits low phase noise (PN) over a wide tuning range (FoM of -184 dBc/Hz and FoMT of -191 dBc/Hz). The PLL occupies 0.09-mm2 core area and exhibits 220-fs RMS jitter while consuming 25 mW,giving FoMRMS of -239 dB. Its settling time improves from 780 to 45 μs with our gear-shift algorithm. For 60-GHz communication,with a frequency multiplication factor of 2.5,this PLL covers all six channel frequencies of IEEE-802.11ad and is capable of supporting 128 QAM and beyond.",

keywords = "Fast-lock phase-locked loop (PLL), IEEE 802.11ad, mm-wave",

author = "Tsai, {Cheng Hsueh} and Federico Pepe and Giovanni Mangraviti and Zhiwei Zong and Jan Craninckx and Piet Wambacq",

year = "2019",

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language = "English",

series = "ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference",

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pages = "111--114",

booktitle = "ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference",

address = "United States",

note = "45th IEEE European Solid State Circuits Conference, ESSCIRC 2019 ; Conference date: 23-09-2019 Through 26-09-2019",

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Tsai, CH, Pepe, F, Mangraviti, G, Zong, Z, Craninckx, J & Wambacq, P 2019, A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter. in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference., 8902868, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., blz. 111-114, 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019, Cracow, Poland, 23/09/19. https://doi.org/10.1109/ESSCIRC.2019.8902868

A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter. / Tsai, Cheng Hsueh; Pepe, Federico; Mangraviti, Giovanni; Zong, Zhiwei; Craninckx, Jan; Wambacq, Piet.

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2019. blz. 111-114 8902868 (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference).

Onderzoeksoutput: Conference paper

TY - GEN

T1 - A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter

AU - Tsai, Cheng Hsueh

AU - Pepe, Federico

AU - Mangraviti, Giovanni

AU - Zong, Zhiwei

AU - Craninckx, Jan

AU - Wambacq, Piet

PY - 2019/9/1

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N2 - We present a 22.5-27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for mm-wave communication. The fast lock is achieved with the help of the proposed gear-shift algorithm,scaling up the PLL bandwidth for faster settling,and orderly reducing it for jitter performance. A digitally controlled oscillator (DCO),based on transformer feedback with a tunable source-bridged capacitor,exhibits low phase noise (PN) over a wide tuning range (FoM of -184 dBc/Hz and FoMT of -191 dBc/Hz). The PLL occupies 0.09-mm2 core area and exhibits 220-fs RMS jitter while consuming 25 mW,giving FoMRMS of -239 dB. Its settling time improves from 780 to 45 μs with our gear-shift algorithm. For 60-GHz communication,with a frequency multiplication factor of 2.5,this PLL covers all six channel frequencies of IEEE-802.11ad and is capable of supporting 128 QAM and beyond.

AB - We present a 22.5-27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for mm-wave communication. The fast lock is achieved with the help of the proposed gear-shift algorithm,scaling up the PLL bandwidth for faster settling,and orderly reducing it for jitter performance. A digitally controlled oscillator (DCO),based on transformer feedback with a tunable source-bridged capacitor,exhibits low phase noise (PN) over a wide tuning range (FoM of -184 dBc/Hz and FoMT of -191 dBc/Hz). The PLL occupies 0.09-mm2 core area and exhibits 220-fs RMS jitter while consuming 25 mW,giving FoMRMS of -239 dB. Its settling time improves from 780 to 45 μs with our gear-shift algorithm. For 60-GHz communication,with a frequency multiplication factor of 2.5,this PLL covers all six channel frequencies of IEEE-802.11ad and is capable of supporting 128 QAM and beyond.

KW - Fast-lock phase-locked loop (PLL)

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T3 - ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference

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BT - ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019

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ER -

Tsai CH, Pepe F, Mangraviti G, Zong Z, Craninckx J, Wambacq P. A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter. In ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc. 2019. blz. 111-114. 8902868. (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2019.8902868

A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter

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Publicatie series

Conference

Toegang tot document

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Projecten

SRP19: Centrum voor modelgebaseerde systeemverbetering - van computer-gerichte engineering tot model-gerichte engineering

Citeer dit