A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC

Lucas Moura Santana, Ewout Martens, Jorge Luis Lagos Benites, Benjamin Hershberg, Piet Wambacq, Jan Craninckx

Onderzoeksoutput: Conference paper

2 Citaten (Scopus)

Samenvatting

This work presents a discrete-time (DT) delta sigma modulator (DSM) ADC that uses ring amplifiers to relax critical speed and efficiency bottlenecks. The DSM is designed as a 3 rd -order Cascade of Integrator with Feed Forward (CIFF) with a 4-bit quantizer, and it achieves a peak SNDR of 67dB and DR of 70.0dB with 47.5MHz bandwidth when clocked at 950MHz. This is the highest bandwidth reported to-date among single-channel DT DSM ADCs and demonstrates a viable alternative to continuous-time (CT) DSM ADCs for wideband oversampling applications. With a power consumption of 4.7mW from a 1V supply, FOMs and FOMw are 167.0dB and 27.0fJ/c.s. respectively, demonstrating efficient DT delta-sigma conversion with high bandwidth.
Originele taal-2English
TitelESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)
Plaats van productieGrenoble, France
UitgeverijIEEE
Pagina's207-210
Aantal pagina's4
ISBN van elektronische versie9781665437479
DOI's
StatusPublished - 13 sep 2021
EvenementIEEE 47th European Solid State Circuits Conference - Grenoble, Grenoble, France
Duur: 13 sep 202117 sep 2021
https://www.esscirc-essderc2021.org/

Publicatie series

NaamESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings

Conference

ConferenceIEEE 47th European Solid State Circuits Conference
Verkorte titelESSCIRC
Land/RegioFrance
StadGrenoble
Periode13/09/2117/09/21
Internet adres

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