TY - GEN
T1 - A 67mW D-band FMCW I/Q Radar Receiver with an N-path Spillover Notch Filter in 28nm CMOS
AU - Kankuppe Raghavendra Swamy, Anirudh
AU - Park, Sehoon
AU - Vaesen, Kristof
AU - Park, Dae-Woong
AU - van Liempd, Barend
AU - Wambacq, Piet
AU - Craninckx, Jan
PY - 2021/9/13
Y1 - 2021/9/13
N2 - A 139.5-157.7 GHz D-band I/Q radar receiver with an on-chip antenna and a spillover resilient N-path baseband filter is presented. Spillover and its manifestation based on the chirp rate is discussed and a filter for spillover mitigation is implemented. The radar is characterized with 55 dB conversion gain, 8dB NF (5.6 dB EINF) and 26dB narrow-band spillover attenuation. The receiver is also capable of selectively mitigating very close by large reflectors and the system power consumption is 67mW.
AB - A 139.5-157.7 GHz D-band I/Q radar receiver with an on-chip antenna and a spillover resilient N-path baseband filter is presented. Spillover and its manifestation based on the chirp rate is discussed and a filter for spillover mitigation is implemented. The radar is characterized with 55 dB conversion gain, 8dB NF (5.6 dB EINF) and 26dB narrow-band spillover attenuation. The receiver is also capable of selectively mitigating very close by large reflectors and the system power consumption is 67mW.
UR - http://www.scopus.com/inward/record.url?scp=85118453862&partnerID=8YFLogxK
U2 - 10.1109/ESSCIRC53450.2021.9567860
DO - 10.1109/ESSCIRC53450.2021.9567860
M3 - Conference paper
T3 - ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings
SP - 471
EP - 474
BT - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021
PB - IEEE
T2 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021
Y2 - 13 September 2021 through 22 September 2021
ER -