A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range

Badr Malki; Takaya Yamamoto; Bob Verbruggen; Piet Wambacq; J. Craninckx

doi:10.1109/JSSC.2014.2309086

A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range

Badr Malki
, Takaya Yamamoto
, Bob Verbruggen
, Piet Wambacq
, J. Craninckx

Elektronica en Informatica

Onderzoeksoutput: Article › peer review

47 Citaten (Scopus)

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A charge-domain SAR ADC is presented which integrates the current of a variable-gain transconductor on its sampling capacitor, rather than being driven by a power hungry voltage buffer. The sampling circuit uses nonlinear MOS capacitors as sampling capacitor for passive amplification to relax the comparator noise requirements without compromising linearity. The prototype in 40 nm low power CMOS process consists of a 1.1-17.6 mS transconductor, combined with a 10 b 0-80 MS/s charge-sharing SAR ADC. It achieves 70 dB DR while consuming less than 5.45 mA from a 1.1 V supply and achieves a peak SNDR of 56.85 dB at 40 MS/s.

Originele taal-2	English
Pagina's (van-tot)	1173 - 1183
Tijdschrift	IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume	49
Nummer van het tijdschrift	5
DOI's	https://doi.org/10.1109/JSSC.2014.2309086
Status	Published - 5 mei 2014

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http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6763107

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SRP19: Centrum voor modelgebaseerde systeemverbetering - van computer-gerichte engineering tot model-gerichte engineering
Vandersteen, G. (Administrative Promotor), Rolain, Y. (Co-Promoter), Wambacq, P. (Co-Promoter), Kuijk, M. (Co-Promoter), Vandersteen, G. (Administrative Promotor), Rolain, Y. (Co-Promoter), Wambacq, P. (Co-Promoter) & Kuijk, M. (Co-Promoter)
1/11/12 → 31/10/24
Project: Fundamenteel

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AU - Craninckx, J.

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A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range

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SRP19: Centrum voor modelgebaseerde systeemverbetering - van computer-gerichte engineering tot model-gerichte engineering

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