A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS

Lucas Moura Santana, Ewout Martens, Jorge Luis Lagos Benites, Benjamin Hershberg, Piet Wambacq, Jan Craninckx

Onderzoeksoutput: Articlepeer review

3 Citaten (Scopus)

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This article presents a delta sigma modulator (DSM) analog to digital (ADC) that uses ring amplifiers as integrators to relax speed and efficiency bottlenecks in discrete-time (DT) oversampled ADCs. Its multi-bit quantizer is based on split source (SS) comparators, adding flexibility and power efficiency. The complete oversampling ADC is designed as a 3rd-order cascade of integrator with feed forward (CIFF) with a 4-bit quantizer, and it achieves a peak signal-to-noise and distortion ratio (SNDR) of 67 dB and DR of 70.0 dB with 47.5-MHz bandwidth when clocked at 950 MHz. This is the highest bandwidth reported to date among single-channel DT DSM ADCs and demonstrates a viable alternative to continuous-time (CT) DSM ADCs for wideband oversampling applications. With a power consumption of 4.7 mW from a 1-V supply, figure of merit (FoM) Schreier and Walden are 167.0 dB and 27.0 fJ/c.s, respectively, demonstrating efficient DT delta-sigma conversion with high bandwidth.
Originele taal-2English
Pagina's (van-tot)2068-2077
Aantal pagina's10
TijdschriftIEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume57
Nummer van het tijdschrift7
DOI's
StatusPublished - 1 jul 2022

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