A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS

Lucas Moura Santana, Ewout Martens, Jorge Luis Lagos Benites, Benjamin Hershberg, Piet Wambacq, Jan Craninckx

Onderzoeksoutput: Articlepeer review

3 Citaten (Scopus)

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