A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS

Lucas Moura Santana, Ewout Martens, Jorge Luis Lagos Benites, Benjamin Hershberg, Piet Wambacq, Jan Craninckx

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  • 2021

    A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC

    Moura Santana, L., Martens, E., Lagos Benites, J. L., Hershberg, B., Wambacq, P. & Craninckx, J., 13 sep 2021, ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC). Grenoble, France: IEEE, blz. 207-210 4 blz. (ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings).

    Onderzoeksoutput: Conference paper

    2 Citaten (Scopus)