A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs

Bao Trong Huynh, Sushil Sakhare, Julien Ryckaert, Dimitri Yakimets, Aaron Thean, Abdelkarim Mercha, Diederik Verkest, Piet Wambacq

Onderzoeksoutput: Article

21 Citaten (Scopus)


In this paper, we present an intensive study of 6T-SRAM designs for vertical gate-all-around (GAA) transistors (VFETs) and lateral GAA transistors (LFETs) using 5-nm node design rules. Optimizations of the nanowire (NW) diameter and the gate length are also conducted to enhance the SRAM performance. Device VT retargeting has been proposed for improving the minimum operating voltage (Vmin) of SRAMs. The isoperformance and isoyield have been performed to assess and determine the benefits provided by LFET and VFET architectures, respectively. Our results show that the VFET bitcells are denser than the LFET bitcells by 20%-30%. The SRAM read stability (read static noise margin) is significantly improved using the NW channel. For a 6σ yield target and an isoarea of SRAM bitcells, Vmin of the VFET bitcell is 80 mV lower than LFET designs. Applying the proposed VT retargeting technique can allow the VFET 122 bitcell to operate at 0.57 V without using assist circuits. A standby leakage below 10 pA/cell can be achieved for both architectures. At isoperformance, the standby leakage of VFET bitcells is 2.6× lower than LFET bitcells.
Originele taal-2English
Pagina's (van-tot)643-651
Aantal pagina's8
TijdschriftIEEE Transactions on Electron Devices
Nummer van het tijdschrift2
StatusPublished - 1 feb 2016


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