Cardiovascular diseases are a leading cause of death globally, and atrial fibrillation (AF) is a common arrhythmia that affects many people. Detecting AF in real-time using hardware acceleration can prompt timely medical intervention. Multi-layer perceptron (MLP) has demonstrated the ability to detect AF accurately. However, implementing MLP on Field-Programmable Gate Array (FPGA) for real-time detection poses challenges due to the complex hardware design requirements. This study presents a novel framework for generating hardware accelerators to detect AF in real-time using MLP on FPGA. The framework automates evaluating MLP model topology, data type, and bit-widths to generate parallel acceleration. The generated solutions are evaluated using two AF datasets, PhysioNet MIT-BIH atrial fibrillation (AFDB) and China Physiological Signal Challenge 2018 (CPSC2018), regarding execution time, resource utilization, and accuracy. The evaluation results demonstrate that the hardware MLP can achieve a speedup higher than 1500× and around 25000× lower energy consumption than an embedded CPU. These satisfactory results prove the framework's suitability and convenience for the online detection of AF in an accelerated and automatic way through FPGA hardware implementation.
|Tijdschrift||IEEE Transactions on Biomedical Circuits and Systems|
|Nummer van het tijdschrift||99|
|Status||Published - 26 jul 2023|
Bibliografische notaPublisher Copyright: