Comparator hysteresis compensation for decision feedback equalizers

Oscar Elisio Mattia, Davide Guermandi, Guy Torfs, Piet Wambacq

Onderzoeksoutput: Article


High-speed comparators are extensively used in serial link receiver designs. Some comparator architectures can show significant hysteresis that degrade the sensitivity of the receiver, increasing the bit error rate. In this Letter, a comparator hysteresis compensation strategy that re-uses the first tap of a decision feedback equaliser to shift the comparator input voltage, increasing the decision margin is proposed. An updated equaliser coefficient adaptation scheme is also introduced. The proposed technique can be used for binary and multi-level modulations.
Originele taal-2English
Pagina's (van-tot)1421-1422
Aantal pagina's2
TijdschriftElectronics Letters
Nummer van het tijdschrift25
StatusPublished - 17 dec 2018


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