Noise Analysis of Constant-Slope Voltage-to-Time Converters

Voltage-to-time converters (VTCs) are critical components in time-domain (TD) analog-to-digital converters (ADCs). This paper addresses a gap in existing literature by analyzing noise in constant-slope (CS) VTCs. Noise contributions are examined across three operational phases: sampling, integration, and crossing-detection. Single-ended (SE) and common-mode (CM) integration approaches are compared, identifying the latter as effective in reducing noise. Moreover, it is shown that while the sampling and integration noise contributions are not affected by the VTC operating speed, faster VTCs suffer from a signal-to-noise ratio (SNR) degradation due to the crossing-detector (CD) noise contribution. Theoretical findings are validated through schematic-level simulations in a 22−nm FDSOI CMOS technology, observing agreement.